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ISL6611AIRZ-T

P1-P3P4-P6P7-P9P10-P12P13-P14
10
FN6881.1
August 28, 2012
pins completes the bootstrap circuit. The ISL6611A’s internal
bootstrap resistor is designed to reduce the overcharging of
the bootstrap capacitor when exposed to excessively large
negative voltage swing at the PHASE node. Typically, such
large negative excursions occur in high current applications
that use D
2
-PAK and D-PAK MOSFETs or excessive layout
parasitic inductance. Equation 1 helps select a proper
bootstrap capacitor size:
where Q
G1
is the amount of gate charge per upper MOSFET
at V
GS1
gate-source voltage and N
Q1
is the number of
control MOSFETs. The ΔV
BOOT_CAP
term is defined as the
allowable droop in the rail of the upper gate drive.
As an example, suppose two HAT2168 FETs are chosen as
the upper MOSFETs. The gate charge, Q
G
, from the data
sheet is 12nC at 5V (V
GS
) gate-source voltage. Then the
Q
GATE
is calculated to be 26.4nC at 5.5V PVCC level. We
will assume a 100mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.264µF is required. The next larger standard value
capacitance is 0.33µF. A good quality ceramic capacitor is
recommended.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
SW
), the output drive impedance, the
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
+125°C. The maximum allowable IC power dissipation for
the 4x4 QFN package, with an exposed heat escape pad, is
around 2W. See “Layout Considerations” on page 12 for
thermal transfer improvement suggestions. When designing
the driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
the driver’s internal circuitry and their corresponding average
driver current can be estimated with Equations 2 and 3,
respectively,
where the gate charge (Q
G1
and Q
G2
) is defined at a
particular gate to source voltage (V
GS1
and V
GS2
) in the
corresponding MOSFET datasheet; I
Q
is the driver’s total
quiescent current with no load at both drive outputs; N
Q1
and N
Q2
are number of upper and lower MOSFETs,
respectively. The factor 2 is the number of active channels.
The I
Q
V
CC
product is the quiescent power of the driver
without capacitive load.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
G1
and R
G2
, should be a short to avoid
interfering with the operation shoot-through protection
circuitry) and the internal gate resistors (R
GI1
and R
GI2
) of
MOSFETs. Figures 3 and 4 show the typical upper and lower
gate drives turn-on transition path. The power dissipation on
the driver can be roughly estimated as Equation 4:
C
BOOT_CAP
Q
GATE
ΔV
BOOT_CAP
--------------------------------------
≥
Q
GATE
Q
G1
PVCC•
V
GS1
------------------------------------
N
Q1
•=
(EQ. 1)
50nC
20nC
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
ΔV
BOOT
(V)
C
BOOT_CAP
(µF)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
Q
GATE
= 100nC
1.8
2.0
(EQ. 2)
P
Qg_Q1
Q
G1
PVCC
2
•
V
GS1
---------------------------------------
F
SW
• N
Q1
•=
P
Qg_Q2
Q
G2
PVCC
2
•
V
GS2
---------------------------------------
F
SW
• N
Q2
•=
P
Qg_TOT
2P
Qg_Q1
P
Qg_Q2
+()• I
Q
VCC•+=
(EQ. 3)
I
DR
2
Q
G1
N
Q1
•
V
GS1
----------------------------- -
Q
G2
N
Q2
•
V
GS2
----------------------------- -
+
⎝⎠
⎜⎟
⎛⎞
• F
SW
I
Q
+•=
(EQ. 4)
P
DR_UP
R
HI1
R
HI1
R
EXT1
+
--------------------------------------
R
LO1
R
LO1
R
EXT1
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
P
Qg_Q1
2
---------------------
•=
P
DR_LOW
R
HI2
R
HI2
R
EXT2
+
--------------------------------------
R
LO2
R
LO2
R
EXT2
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
P
Qg_Q2
2
---------------------
•=
R
EXT2
R
G1
R
GI1
N
Q1
-------------
+=
R
EXT2
R
G2
R
GI2
N
Q2
-------------
+=
P
DR
2P
DR_UP
P
DR_LOW
+()• I
Q
VCC•+=
ISL6611A
11
FN6881.1
August 28, 2012
EN_PH Operation
The ISL6611A disables the phase doubler operation when the
EN_PH pin is pulled to ground and after it sees the PWM
falling edge. The PWM pin is pulled to VCC at the PWM falling
edge. With the PWM line pulled high, the controller will disable
the corresponding phase and the higher number phases.
When the EN_PH is pulled high, the phase doubler will pull
the PWM line to tri-state and then will be enabled at the
leading edge of PWM input. Prior to a leading edge of PWM, if
the PWM is low, both LGATEA and LGATEB remain in
tri-state unless the corresponding phase node (PHASEA,
PHASEB) is higher than 80% of VCC. This provides additional
protection if the doubler is enabled while the high-side
MOSFET is shorted. However, this feature limits the
pre-charged output voltage to less than 80% of VCC. Note
that the first doubler should always tie its EN_PH pin high
since Intersil controllers do not allow PWM1 pulled high and
this channel should remain ON to protect the system from an
overvoltage event even when the controller is disabled.
SYNC Operation
The ISL6611A can be set to interleaving mode or
synchronous mode by pulling the SYNC pin to GND or VCC,
respectively. A synchronous pulse can be sent to the phase
doubler during the load application to improve the voltage
droop and current balance while it still can maintain
interleaving operation at DC load conditions. However, an
excessive ringback can occur; hence, the synchronous
mode operation could have drawbacks. Figure 6 shows how
to generate a synchronous pulse only when an transient
load is applied. The comparator should be a fast comparator
with a minimum delay.
Current Balance and Maximum Frequency
The ISL6611A utilizes r
DS(ON)
sensing technique to balance
both channels, while the sample and hold circuits refer to
GND pin. The phase current sensing resistors are
integrated, while the current gain can be scaled by the
impedance on the IGAIN pin, as shown in Table 1. In most
applications, the default option should just work fine.
In addition to balancing the effective UGATE pulse width of
phase A and phase B via standard r
DS(ON)
current sensing
technique, a fast path is also added to swap both channels’
firing order when one phase carries much higher current
than the other phase. This improves the current balance
between phase A and phase B during high frequency load
transient events.
Each phase starts to sample current 200ns (t
BLANK
) after
LGATE falls and lasts for 400ns (t
SAMP
) or ends at the rising
edge of PWM if the available sampling time (t
AVSAMP
) is
< 400ns. The available sampling time (t
AVSAMP
) depends
upon the blanking time (t
BLANK
), the duty cycle (D), the
rising and falling time of low-side gate drive (t
LR
, t
LF
), the
total propagation delay (t
PD
= t
PDLL
+ t
PDLU
), and the
switching frequency (F
SW)
. As the switching frequency and
the duty cycle increase, the available sampling time could be
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Q1
D
S
G
R
GI1
R
G1
BOOT
R
HI1
C
DS
C
GS
C
GD
R
LO1
PHASE
PVCC
UGATE
PVCC
Q2
D
S
G
R
GI2
R
G2
R
HI2
C
DS
C
GS
C
GD
R
LO2
GND
LGATE
FIGURE 5. TYPICAL EN_PH OPERATION TIMING DIAGRAM
EN_PH
PWM
UGATE
LGATE
TABLE 1. CURRENT GAIN SELECTION
IMPEDANCE TO GND CURRENT GAIN
OPEN DEFAULT
0Ω DEFAULT/2
49.9kΩ DEFAULT/5
FIGURE 6. TYPICAL SYNC PULSE GENERATOR
+
-
COMP
SYNC
1.0 nF
2k
Ω
20kΩ
49.9kΩ
1kΩ
VCC
0 Ω
DNP
ISL6611A
12
FN6881.1
August 28, 2012
< 400ns. For a good current balance, it is recommended to
keep at least 200ns sampling time, if not the full 400ns.
Equations 5 and 6 show the maximum frequency of each
channel in interleaving mode and synchronous mode,
respectively. Assume 80ns each for t
PD
, t
LR
, t
LF
and 200ns
each for t
AVSAMP
, t
BLANK
, the maximum channel frequency
can be set to no more than 500kHz at interleaving mode and
1MHz at synchronous mode, respectively, for an application
with a maximum duty cycle of 20%. The maximum duty cycle
occurs at the maximum output voltage (overvoltage trip level
as needed) and at the minimum input voltage (undervoltage
trip level as needed). The efficiency of the voltage regulator
is also a factor in the theoretical approximation. Figure 7
shows the relationship between the maximum channel
frequency and the maximum duty cycle in the previous
assumed conditions.
For interleaving mode (SYNC = “0”),
For synchronous mode (SYNC = “1”),
Note that the PWM controller should be set to 2 x F
SW
for
interleaving mode and the same switching frequency for the
synchronous mode.
Application Information
MOSFET and Driver Selection
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
cause serious ringing, exceeding absolute maximum rating
of the devices. The negative ringing at the edges of the
PHASE node could increase the bootstrap capacitor voltage
through the internal bootstrap diode, and in some cases, it
may overstress the upper MOSFET driver. Careful layout,
proper selection of MOSFETs and packaging, as well as the
proper driver can go a long way toward minimizing such
unwanted stress.
The selection of D
2
-PAK, or D-PAK packaged MOSFETs, is
a much better match (for the reasons discussed) for the
ISL6611A with a phase resistor (R
PH
), as shown in Figure 8.
Low-profile MOSFETs, such as Direct FETs and multi-source
leads devices (SO-8, LFPAK, PowerPAK), have low parasitic
lead inductances and can be driven by ISL6611A (assuming
proper layout design) without the phase resistor (R
PH
).
Layout Considerations
A good layout helps reduce the ringing on the switching
node (PHASE) and significantly lower the stress applied to
the output drives. The following advice is meant to lead to an
optimized layout and performance:
• Keep decoupling loops (VCC-GND, PVCC-PGND and
BOOT-PHASE) short and wide, at least 25 mils. Avoid
using vias on decoupling components other than their
ground terminals, which should be on a copper plane with
at least two vias.
• Minimize trace inductance, especially on low-impedance
lines. All power traces (UGATE, PHASE, LGATE, PGND,
PVCC, VCC, GND) should be short and wide, at least
25 mils. Try to place power traces on a single layer,
otherwise, two vias on interconnection are preferred
where possible. For no connection (NC) pins on the QFN
(EQ. 5)
F
SW
MAX()
12DMAX()⋅–
t
AVSAMP
t
PD
t
LR
t
LF
t
BLANK
++++()2⋅
----------------------------------------------------------------------------------------------------------------
≈
DMAX()
VOUT MAX()
VIN MIN()η⋅
-------------------------------------
≈
(EQ. 6)
F
SW
MAX()
1DMAX()–
t
AVSAMP
t
PD
t
LR
t
LF
t
BLANK
++++()
--------------------------------------------------------------------------------------------------------
≈
FIGURE 7. MAXIMUM CHANNEL SWITCHING FREQUENCY
vs MAXIMUM DUTY CYCLE IN ASSUMED
CONDITIONS
0.1
1
10
0 20406080100
DUTY CYCLE (%)
F
SW
(MHz)
SYNCHRONOUS
INTERLEAVING
FIGURE 8. PHASE RESISTOR TO MINIMIZE SERIOUS
NEGATIVE PHASE SPIKE IF NEEDED
Q1
D
S
G
R
PH
= 1Ω TO 2Ω
BOOT
R
HI1
R
LO1
PHASE
PVCC
UGATE
ISL6611A
P1-P3P4-P6P7-P9P10-P12P13-P14

ISL6611AIRZ-T

Mfr. #:
Buy ISL6611AIRZ-T
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers PHS DOUBLER INTEGRTD 5V DRVRS 3OHM R BOOT
Lifecycle:
New from this manufacturer.
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