6.42
19
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
Boundary Scan Exit Order (1M x 18-Bit)
ORDER PIN ID
16R
26P
36N
47P
57N
67R
78R
88P
99R
10 11P
11 10P
12 10N
13 9P
14 10M
15 11N
16 9M
17 9N
18 11L
19 11M
20 9L
21 10L
22 11K
23 10K
24 9J
25 9K
26 10J
27 11J
28 11H
29 10G
30 9G
31 11F
32 11G
33 9F
34 10F
35 11E
36 10E
6112 tbl 16
ORDER PIN ID
37 10D
38 9E
39 10C
40 11D
41 9C
42 9D
43 11B
44 11C
45 9B
46 10B
47 11A
48 Internal
49 9A
50 8B
51 7C
52 6C
53 8A
54 7A
55 7B
56 6B
57 6A
58 5B
59 5A
60 4A
61 5C
62 4B
63 3A
64 1H
65 1A
66 2B
67 3B
68 1C
69 1B
70 3D
71 3C
72 1D
6112 tbl 17
ORDER PIN ID
73 2C
74 3E
75 2D
76 2E
77 1E
78 2F
79 3F
80 1G
81 1F
82 3G
83 2G
84 1J
85 2J
86 3K
87 3J
88 2K
89 1K
90 2L
91 3L
92 1M
93 1L
94 3N
95 3M
96 1N
97 2M
98 3P
99 2N
100 2P
101 1P
102 3R
103 4R
104 4P
105 5P
106 5N
107 5R
6112 tbl 18
6.4220
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
ORDER PIN ID
16R
26P
36N
47P
57N
67R
78R
88P
99R
10 11P
11 9P
12 10N
13 10P
14 11M
15 9N
16 9M
17 11N
18 11L
19 10L
20 9L
21 10M
22 11K
23 9K
24 9J
25 10K
26 11J
27 9G
28 11H
29 10G
30 10J
31 11F
32 10F
33 9F
34 11G
35 11E
36 9E
6112 tbl 16b
ORDER PIN ID
37 10D
38 10E
39 11C
40 9D
41 9C
42 11D
43 11B
44 10B
45 9B
46 10C
47 11A
48 Internal
49 9A
50 8B
51 7C
52 6C
53 8A
54 7A
55 7B
56 6B
57 6A
58 5B
59 5A
60 4A
61 5C
62 4B
63 3A
64 1H
65 1A
66 3B
67 1B
68 1C
69 2B
70 3D
71 2C
72 1D
6112 tbl 17b
ORDER PIN ID
73 3C
74 3E
75 1E
76 2E
77 2D
78 3F
79 1F
80 1G
81 2F
82 3G
83 2J
84 1J
85 2G
86 3K
87 1K
88 2K
89 3J
90 3L
91 1L
92 1M
93 2L
94 3N
95 2M
96 1N
97 3M
98 3P
99 1P
100 2P
101 2N
102 3R
103 4R
104 4P
105 5P
106 5N
107 5R
6112 tbl 18b
Boundary Scan Exit Order (512K x 36-Bit)
6.42
21
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
Parameter Symbol Min Ty p Max Unit Note
Output Power Supply V
DDQ
1.4 - 1.9 V
Power Supply Voltage V
DD
1.7 1.8 1.9 V
Input High Level V
IH
1.3 - V
DD
+0.3 V
Input Low Level V
IL
-0.3 - 0.5 V
Output High Voltage (I
OH
= -1mA) V
OH
V
DDQ -
0.2 - V
DDQ
V
1
Output Low Voltage (I
OL
= 1mA) V
OL
V
SS
-0.2V
1
6112 tbl 19
Parameter Symbol Min Unit Note
Input High/Low Level V
IH
/V
IL
1.3/0.5 V
Input Rise/Fall Time TR/TF 1.0/1.0 ns
Input and Output Timing Reference Level V
DDQ
/2 V 1
6112 tbl 20
JTAG DC Operating Conditions
JTAG AC Test Conditions
Parameter Symbol Min Max Unit Note
TCK Cycle Time t
CHCH
50 - ns
TCK High Pulse Width t
CHCL
20 - ns
TCK Low Pulse Width t
CLCH
20 - ns
TMS Input Setup Time t
MVCH
5-ns
TMS Input Hold Time t
CHMX
5-ns
TDI Input Setup Time t
DVCH
5-ns
TDI Input Hold Time t
CHDX
5-ns
SRAM Input Setup Time t
SVCH
5-ns
SRAM Input Hold Time t
CHSX
5-ns
Clock Low to Output Valid t
CLQV
010ns
6112 tbl.21
JTAG AC Characteristics
JTAG Timing Diagram
NOTE:
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ.
TC
K
TM
S
t
C
H
C
H
TD
I
/
SR
A
M
Inp
u
t
s
T
D
O
t
M
V
C
H
t
D
V
C
H
t
S
V
C
H
t
C
H
C
L
t
C
H
M
X
t
C
H
D
X
t
C
H
S
X
t
C
L
C
H
t
C
L
Q
V
6112drw 19
SRA
M
Out
p
u
t
s
NOTE:
1. See AC test load on page 12.

IDT71P71804S200BQ

Mfr. #:
Manufacturer:
Description:
IC SRAM 18M PARALLEL 165CABGA
Lifecycle:
New from this manufacturer.
Delivery:
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