6.42
21
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
Parameter Symbol Min Ty p Max Unit Note
Output Power Supply V
1.4 - 1.9 V
Power Supply Voltage V
1.7 1.8 1.9 V
Input High Level V
1.3 - V
+0.3 V
Input Low Level V
-0.3 - 0.5 V
Output High Voltage (I
= -1mA) V
V
0.2 - V
V
1
Output Low Voltage (I
= 1mA) V
V
-0.2V
1
6112 tbl 19
Parameter Symbol Min Unit Note
Input High/Low Level V
IH
/V
IL
1.3/0.5 V
Input Rise/Fall Time TR/TF 1.0/1.0 ns
Input and Output Timing Reference Level V
DDQ
/2 V 1
6112 tbl 20
JTAG DC Operating Conditions
JTAG AC Test Conditions
Parameter Symbol Min Max Unit Note
TCK Cycle Time t
50 - ns
TCK High Pulse Width t
20 - ns
TCK Low Pulse Width t
20 - ns
TMS Input Setup Time t
5-ns
TMS Input Hold Time t
5-ns
TDI Input Setup Time t
5-ns
TDI Input Hold Time t
5-ns
SRAM Input Setup Time t
5-ns
SRAM Input Hold Time t
5-ns
Clock Low to Output Valid t
010ns
6112 tbl.21
JTAG AC Characteristics
JTAG Timing Diagram
NOTE:
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ.
t
t
t
t
t
t
t
t
t
t
6112drw 19
NOTE:
1. See AC test load on page 12.