6.42
9
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
NOTES:
1) All byte write (BWx) and nibble write (NWx) signals are sampled on the
rising edge of K and again on K. The data that is present on the data bus in the
designated byte/nibble will be latched into the input if the corresponding BWx or
NWx is held low. The rising edge of K will sample the first byte/nibble of the
two word burst and the rising edge of K will sample the second byte/nibble of
the two word burst.
2) The availability of the BWx or NWx on designated devices is described in
the pin description table.
3) The DDRII Burst of two SRAM has data forwarding. A read request that is
initiated on the cycle following a write request to the same address will produce
the newly written data.
BW
0
BW
1
BW
2
BW
3
NW
0
NW
1
Write Byte 0 LXXXXX
Write Byte 1 X L X X X X
Write Byte 2 X X L X X X
Write Byte 3 XXXLXX
Write Nibble 0 X X X X L X
Write Nibble 1 XXXXXL
6112 tbl 09
Write Descriptions
(1,2)
Linear Burst Sequence Table
(1,2)
NOTE:
1. SA0 is the address presented giving the burst sequence a,b.
2. SA0 is only available on the x18 and x36-bit devices.
ab
01
10
6112 tbl 22