RE46C107
DC to DC Converter, Voltage Regulator and R&E International
Piezoelectric Horn Driver
A Subsidiary of Microchip Technology Inc.
Product Specification
© 2009 Microchip Technology Inc. DS22160A-page 2
PIN DESCRIPTIONS
PIN# PIN NAME DESCRIPTION
1 LBST Logic input used to activate low battery detection circuitry. This includes activating high
boost mode. Input is designed to interface with circuitry supplied by Vreg, so input voltage
levels will scale with the Vreg voltage. Input is disabled during brown-out.
2 LBSET Internally connected to the low battery comparator input used to sense the Vdd voltage
divider. The internal reference to which this node is compared is nominally 0.9V. Nominal
internal resistance to Vdd is 400kohm. Nominal resistance to Vss is 240kohm. The
resistance to Vss is changed to a nominal of 220kohm once a low battery condition is
detected. External resistances can be added in parallel to adjust the low battery threshold
voltage.
3 VDD Connect to the positive supply voltage
4 LEDEN Logic input used to enable the LED driver. Input is designed to interface with circuitry
supplied by Vreg, so input voltage levels will scale with the Vreg voltage. LED driver is
disabled during brown-out.
5 LED Open drain NMOS output used to drive a visible LED.
6 LX Open drain NMOS output used to drive the boost converter inductor. The inductor should
be connected from this pin to the positive supply through a low resistance path.
7 VSS2 Internally connected to the source of the NMOS device used to drive the boost converter
inductor. Connect to the negative supply voltage through a low resistance path.
8 VSS Connect to the negative supply voltage.
9 REGSEL Logic input used to set the Vreg output voltage level. This input should always be tied to
either Vdd or Vss.
10 VREG Regulated output voltage. Nominal output is 3.3V for REGSEL=Vdd and 3.0V for
REGSEL=Vss.
11 VO Boosted voltage produced by DC-DC converter, typically 4V or 10V.
12 HORNB This pin is connected to the metal electrode (B) of a piezoelectric transducer.
13 HORNS HS is a complementary output to HB and connects to the ceramic electrode (S) of the
piezoelectric transducer.
14 HRNEN Logic input for horn enable designed to interface with circuitry supplied by Vreg. Input
voltage levels will scale with the Vreg voltage. Horn is disabled during brown-out.
15 FEED Usually connected to the feedback electrode of the piezoelectric horn through a current
limiting resistor. If not used, this pin must be connected to Vss.
16 LBOUT Logic output used to signal a low battery condition. Output pulls to Vreg when LBST is
high and a low battery condition is detected.
