AD8522
input register and transferring the 12 bits of data into the de-
coded address determined by the address bits A and B in the se-
rial input register.
Unipolar Output Operation
This is the basic mode of operation for the AD8522. The
AD8522 has been designed to drive loads as low as 820 Ω in
parallel with 500 pF. The code table for this operation is shown
in Table III.
Table III. Unipolar Code Table
Hexadecimal Decimal Analog
Number in Number in Output
DAC Register DAC Register Voltage (V)
FFF 4095 +4.095
801 2049 +2.049
800 2048 +2.048
7FF 2047 +2.047
000 0 0
5
2
0
1
3
4
10 100 100k10k1k
R
L
TIED TO AGND
DATA = FFF
H
V
DD
= +5V
T
A
= +25
°
C
R
L
TIED TO +5V
DATA = 000
H
LOAD RESISTANCE – Ω
OUTPUT VOLTAGE – Volts
V
IN
H = +5V
V
IN
L = 0V
Figure 6. Output Swing vs. Load
80
60
40
20
0
–20
–40
–60
–80
123
OUTPUT VOLTAGE – Volts
OUTPUT CURRENT – mA
DATA = 800
H
POSITIVE
CURRENT
LIMIT
NEGATIVE
CURRENT
LIMIT
Figure 9. I
OUT
vs. V
OUT
5.2
5.0
4.8
4.6
4.4
4.2
4.0
0.01
0.1 100101.0
OUTPUT LOAD CURRENT – mA
V
DD
MIN – Volts
∆V
FS
≤ 1 LSB
DATA = FFF
H
T
A
= +25°C
PROPER OPERATION
WHEN V
DD
SUPPLY
VOLTAGE IS ABOVE
CURVE
Figure 7. Minimum Supply Voltage
vs. Load Current
100
90
10
0%
200µV/DIV
100µs/DIV
T
A
= +25°C
NBW = 1MHz
Figure 10. Broadband Noise
1 10 1000100
100
1
0.1
10
0.01
+85°C
–55°C
+25°C
V
DD
= +5V
DATA = 000
H
V
IH
= 5.0V
V
IL
= 0.0V
OUTPUT SINK CURRENT – µA
OUTPUT PULL-DOWN VOLTAGE – mV
Figure 8. Pull-Down Voltage vs. Out-
put Sink Current Capability
9
8
7
6
5
4
3
2
1
0
01 3452
V
DD
= +4.5V
V
DD
= +5V
T
A
= +25°C
SUPPLY CURRENT I
DD
– mA
LOGIC INPUT VOLTAGE V
IN
H – Volts
Figure 11. Supply Current vs. Logic
Input Voltage
Typical Performance Characteristics
is possible down to +4.3 V. The minimum operating supply
voltage versus load current plot, in Figure 7, provides informa-
tion for operation below V
DD
= +4.5 V.
TIMING AND CONTROL
The AD8522 has a 16-bit serial input register that accepts
clocked in data when the CS pin is active low. The DAC regis-
ters are updated by the Load Enable (
LDA and LDB) pins.
The AD8522 offers two modes of data loading. The first mode,
hardware-load, directs the data currently clocked into the serial
shift register into either the DAC A or the DAC B register or
both depending on the external active low strobing of the
LDA
or
LDB pin. Serial data register bit Sf/Hd must be low for this
mode to be in effect.
The second mode of operation is software-load which is de-
signed to minimize the number of control lines connected to
the AD8522. In this mode of operation the
LDA and LDB pins
act as one control input taking the present contents of the serial
–6–
REV. A
