MK1726-08S

DATASHEET
SPREAD SPECTRUM CLOCK GENERATOR MK1726-08
IDT™
SPREAD SPECTRUM CLOCK GENERATOR 1
MK1726-08 REV C 121809
Description
The MK1726-08 generates a low EMI output clock and a
reference clock from a clock or crystal input. The part is
designed to lower EMI through the application of spreading
a clock. Using IDT’ proprietary mix of analog and digital
Phase-Locked Loop (PLL) technology, the device spreads
the frequency spectrum of the output, reducing the
frequency amplitude peaks by several dB depending on
spread range. The MK1726-08 offers a range of down
spread from a high speed clock or crystal input. The
MK1726-08 generates one modulated (SSCLK) and
unmodulated (REFCLK) clock and is compatible with
Cypress CY25819. The modulated clock is controlled by
the select pin, and the unmodulated clock has the same
frequency as the input clock or crystal.
Features
Packaged in 8-pin SOIC
Available in Pb (lead) free package
Input frequency range 16- 32 MHz
Provides modulated and unmodulated clocks
Accepts a clock or crystal input
Provides down spread modulation
Provides power down function
Reduce electromagnetic interference (EMI) by
8-16 db
Operating voltage of 3.3 V
Advanced, low-power CMOS process
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
PLL Clock
Synthesis and
Spread
Spectrum
Circuitry
S0
GND
Clock Buffer/
Crystal
Ocsillator
X1/CLK
X2
External caps required for
with crystal for accurate
tuning of the clock
SSCLK
REFCLK
VDD
PD
MK1726-08
SPREAD SPECTRUM CLOCK GENERATOR SSCG
IDT™
SPREAD SPECTRUM CLOCK GENERATOR 2
MK1726-08 REV C 121809
Pin Assignment Spread Percentage Select Table
0 = connect to GND
M= unconnected
1 = connect directly to VDD
* Default has internal pull up resitor to VDD
Pin Descriptions
X1/ICLK
GND
S0
VDD
SSCLK
PD
REFCLK
X21
2
3
4
8
7
6
5
8 pin (150mil) SOIC
S0 Spread
Direction
Spread
Percentage (%)
0Down -1.8
1Down -2.5
MDown -0.6
Pin
Number
Pin
Name
Pin Type Pin Description
1 X1/ICLK Input Connect to 16-32 MHz crystal or clock.
2 GND Power Connect to ground.
3 S0 Input Select spread percentage per table above. Internal pull-up.
4 SSCLK Output Spread spectrum clock output per table above.
5 REFCLK Power CMOS level clock output matches the nominal frequency of the input crystal or
clock.
6PD
Input Power down tri-state. This pin powers down entire chip and tri-state the outputs
when low. Internal pull-up.
7 VDD Power Connect to 3.3 V.
8 X2 Input Connect to 16-32 MHz crystal or leave unconnected.
MK1726-08
SPREAD SPECTRUM CLOCK GENERATOR SSCG
IDT™
SPREAD SPECTRUM CLOCK GENERATOR 3
MK1726-08 REV C 121809
External Components
The MK1726-08 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the load
is over 1 inch, series termination should be used. To series
terminate a 50 trace (a commonly used trace impedance)
place a 33 resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) To minimize EMI, the 33 series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
MK1726-08. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Crystal caps (pF) = (C
L
- 6) x 2
In the equation, C
L
is the crystal load capacitance. So, for a
crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2]
capacitors should be used.
Spread Spectrum Profile
The MK1726-08 low EMI clock generator uses an optimized
frequency slew rate algorithm to facilitate down stream
tracking of zero delay buffers and other PLL devices. The
frequency modulation amplitude is constant with variations
of the input frequency.
Time
Frequency
Modulation Rate

MK1726-08S

Mfr. #:
Manufacturer:
Description:
IC CLK GEN SPREAD SPECTRUM 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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