ICS844N234I Preliminary Data Sheet FEMTOCLOCK NG® CRYSTAL-TO-LVDS CLOCK SYNTHESIZER
ICS844N234AKILF
FEBRUARY 8, 2012
11 ©2012 Integrated Device Technology, Inc.
Applications Information
Interface to IDT SRIO Switches
The ICS844N234I is designed for driving the differential reference
clock input (REF_CLK) of IDT’s SRIO 1.3 and 2.0 switch devices.
The LVDS outputs of the ICS844N234I have the low-jitter, differential
voltage and impedance characteristics required to provide a
high-quality 156.25MHz clock signal for both SRIO 1.3 and 2.0 switch
devices. Please refer to Figure 1 for suggested interfaces. In Figure
1, the AC-coupling capacitors are mandatory by the IDT SRIO switch
devices. The differential REF_CLK_P/N input is internally re-biased
and AC-terminated. Both interface circuits are optimized for 50
transmission lines and generate the voltage swing required to reliably
drive the clock reference input of a IDT SRIO switch. Please refer to
IDT’s SRIO device datasheet for more details.
Figure 1 shows the recommended interface circuit for driving the
156.25MHz reference clock of an IDT SRIO 2.0 switch by a LVDS
output (QA0, QA1, QB0 or QB1) of the ICS844N234I. The
LVDS-to-differential interface as shown in Figure 1 does not require
any external termination resistors: the ICS844N234I driver contains
an internal source termination at all outputs. The differential
REF_CLK input contains an internal AC-termination (R
L
) and re-bias
(V
BIAS
). Use the LVDS Driver Termination (figure 5A and 5B) if the
receiving device does not implement and internal termination.
Figure 1. LVDS-to-SRIO 2.0 Reference Clock Interface
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS844N234I provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V
DD
, V
DDA
, V
DDOA
and V
DDOB
should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 2
illustrates this for a generic V
DD
pin and also shows that V
DDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the V
DDA
pin.
Figure 2. Power Supply Filtering
+
-
REF_CLK
ICS844N234I
IDT SRIO 1.3, 2.0 Switch
L
I
L
I
C
I
C
I
V
BIAS
R
L
R
L
QAn
nQAn
T=50
LVDS
REF_CLK_P
REF_CLK_N
V
CC
V
CCA
3.3V or 2.5V
10Ω
10µF.01µF
.01µF
