NCP5304
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13
Figure 44. I
CC1
Consumption vs. Switching
Frequency with 15 nC Load on Each Driver @
V
CC
= 15 V
0
5
10
15
20
25
0 100 200 300 400 500 600
R
GATE
= 0 R to 22 R
C
LOAD
= 1 nF/Q = 15 nC
I
CC
+ I
BOOT
CURRENT SUPPLY (mA)
SWITCHING FREQUENCY (kHz)
0
5
10
15
20
25
30
35
40
0 100 200 300 400 500 6
00
R
GATE
= 0 R to 22 R
SWITCHING FREQUENCY (kHz)
I
CC
+ I
BOOT
CURRENT SUPPLY (mA)
Figure 45. I
CC1
Consumption vs. Switching
Frequency with 33 nC Load on Each Driver @
V
CC
= 15 V
C
LOAD
= 2.2 nF/Q = 33 nC
0
10
20
30
40
50
60
70
0 100 200 300 400 500 600
I
CC
+ I
BOOT
CURRENT SUPPLY (mA)
SWITCHING FREQUENCY (kHz)
Figure 46. I
CC1
Consumption vs. Switching
Frequency with 50 nC Load on Each Driver @
V
CC
= 15 V
R
GATE
= 0 R to 22 R
C
LOAD
= 3.3 nF/Q = 50 nC
0
20
40
60
80
100
120
0 100 200 300 400 500 6
00
SWITCHING FREQUENCY (kHz)
Figure 47. I
CC1
Consumption vs. Switching
Frequency with 100 nC Load on Each Driver @
V
CC
= 15 V
C
LOAD
= 6.6 nF/Q = 100 nC
I
CC
+ I
BOOT
CURRENT SUPPLY (mA)
R
GATE
= 0 R
R
GATE
= 10 R
R
GATE
= 22 R
Figure 48. NCP5304, Negative Voltage Safe Operating Area on the Bridge Pin
−35
−30
−25
−20
−15
−10
−5
0
0 100 200 300 400 500 600
−40°C
25°C
125°C
NEGATIVE PULSE VOLTAGE (V)
NEGATIVE PULSE DURATION (ns)
NCP5304
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14
APPLICATION INFORMATION
Negative Voltage Safe Operating Area
When the driver is used in a half bridge configuration, it
is possible to see negative voltage appearing on the bridge
pin (pin 6) during the power MOSFETs transitions. When
the high−side MOSFET is switched off, the body diode of
the low−side MOSFET starts to conduct. The negative
voltage applied to the bridge pin thus corresponds to the
forward voltage of the body diode. However, as pcb copper
tracks and wire bonding introduce stray elements
(inductance and capacitor), the maximum negative voltage
of the bridge pin will combine the forward voltage and the
oscillations created by the parasitic elements. As any
CMOS device, the deep negative voltage of a selected pin
can inject carriers into the substrate, leading to an erratic
behavior of the concerned component. ON Semiconductor
provides characterization data of its half−bridge driver to
show the maximum negative voltage the driver can safely
operate with. To prevent the negative injection, it is the
designer duty to verify that the amount of negative voltage
pertinent to his/her application does not exceed the
characterization curve we provide, including some safety
margin.
In order to estimate the maximum negative voltage
accepted by the driver, this parameter has been
characterized over full the temperature range of the
component. A test fixture has been developed in which we
purposely negatively bias the bridge pin during the
freewheel period of a buck converter. When the upper gate
voltage shows signs of an erratic behavior, we consider the
limit has been reached.
Figure 48, illustrates the negative voltage safe operating
area. Its interpretation is as follows: assume a negative
10 V pulse featuring a 100 ns width is applied on the bridge
pin, the driver will work correctly over the whole die
temperature range. Should the pulse swing to −20 V,
keeping the same width of 100 ns, the driver will not work
properly or will be damaged for temperatures below
125°C.
Summary:
If the negative pulse characteristic (negative voltage
level & pulse width) is above the curves the driver
runs in safe operating area.
If the negative pulse characteristic (negative voltage
level and pulse width) is below one or all curves the
driver will NOT run in safe operating area.
Note, each curve of the Figure 48 represents the negative
voltage and width level where the driver starts to fail at the
corresponding die temperature.
If in the application the bridge pin is too close of the safe
operating limit, it is possible to limit the negative voltage
to the bridge pin by inserting one resistor and one diode as
follows:
D1
MUR160
R1
10R
D4
MUR160
C2
100n
M3
M4
0
Vbulk
IN_LO
IN_Hi
0
Vcc
U2
NCP5304
IN_LO
1
IN_HI
2
VCC
3
GND
4
DRV_LO
5
BRIDGE
6
DRV_HI
7
BOOT
8
Figure 49. R1 and D1 Improves the Robustness of the
Driver
R1 and D1 should be placed as close as possible of the
driver. D1 should be connected directly between the bridge
pin (pin 6) and the ground pin (pin 4). By this way the
negative voltage applied to the bridge pin will be limited
by D1 and R1 and will prevent any wrong behavior.
NCP5304
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15
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE N
14
58
b2
NOTE 8
D
b
L
A1
A
eB
E
A
TOP VIEW
C
SEATING
PLANE
0.010 CA
SIDE VIEW
END VIEW
END VIEW
WITH LEADS CONSTRAINED
DIM MIN MAX
INCHES
A −−−− 0.210
A1 0.015 −−−−
b 0.014 0.022
C 0.008 0.014
D 0.355 0.400
D1 0.005 −−−−
e 0.100 BSC
E 0.300 0.325
M −−−− 10
−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
9.02 10.16
0.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAX
MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT
TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −− 10.92
0.060 TYP 1.52 TYP
E1
M
8X
c
D1
B
A2 0.115 0.195 2.92 4.95
L 0.115 0.150 2.92 3.81
°°
H
NOTE 5
e
e/2
A2
NOTE 3
M
B
M
NOTE 6
M

NCP5304PG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers HIGH VOLT MOSFET DR LO MOSFET IGBT DRVR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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