LT3506/LT3506A
17
3506afc
Shorted Input Protection
If the inductor is chosen so that it won’t saturate exces-
sively, the LT3506 will tolerate a shorted output. There is
another situation to consider in systems where the output
will be held high when the input to the LT3506 is absent.
If the V
IN
and one of the RUN/SS pins are allowed to fl oat,
then the LT3506’s internal circuitry will pull its quiescent
current through its SW pin. This is fi ne if your system can
tolerate a few mA of load in this state. With both RUN/SS
pins grounded, the LT3506 enters shutdown mode and
the SW pin current drops to ~30A. However, if the V
IN
pin
is grounded while the output is held high, then parasitic
diodes inside the LT3506 can pull large currents from the
output through the SW pin and the V
IN
pin. A Schottky
diode in series with the input to the LT3506 will protect
the LT3506 and the system from a shorted or reversed
input, as shown in Figure 6.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 7
shows the high-di/dt paths in the buck regulator circuit.
Note that large, switched currents fl ow in the power switch,
the catch diode and the input capacitor. The loop formed by
these components should be as small as possible. These
components, along with the inductor and output capacitor,
should be placed on the same side of the circuit board,
and their connections should be made on that layer. Place
a local, unbroken ground plane below these components,
and tie this ground plane to system ground at one location,
ideally at the ground terminal of the output capacitor C2.
Additionally, the SW and BOOST nodes should be kept as
small as possible. Figure 8 shows recommended compo-
nent placement with trace and via locations.
Thermal Considerations
The PCB must also provide heat sinking to keep the LT3506
cool. The exposed metal on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to other copper layers below with thermal vias;
these layers will spread the heat dissipated by the LT3506.
Place additional vias near the catch diodes. Adding more
copper to the top and bottom layers and tying this cop-
per to the internal planes with vias can reduce thermal
resistance further. With these steps, the thermal resis-
tance from die (or junction) to ambient can be reduced to
θ
JA
= 43°C/W.
The power dissipation in the other power components—
catch diodes, boost diodes and inductors, cause additional
copper heating and can further increase what the IC sees
as ambient temperature. See the LT1767 data sheet’s
Thermal Considerations section.
VIA TO LOCAL GROUND PLANE
VIA TO V
IN
PIN 1
TOP MARK
3506 F08
GNDV
OUT1
V
OUT2
Figure 8. A Good PCB Layout Ensures Proper Low EMI Operation
APPLICATIONS INFORMATION
