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PCA9556
Octal SMBus and I
2
C registered interface
Product data
Supersedes data of 2000 Nov 13
2002 Mar 28
INTEGRATED CIRCUITS
Philips Semiconductors Product data
PCA9556Octal SMBus and I
2
C registered interface
2
2002 Mar 28 853-2138 27929
FEATURES
SMBus compliance with fixed 3.3V voltage levels
Operating power supply voltage range of 3.0 V – 5.5 V
Active high polarity inverter register
Each I/O is configurable as an input or output
Active low reset pin
Low leakage current on power-down
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
8 I/O pins which default to 8 inputs
High impedance open drain on I/O0
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
DESCRIPTION
The PCA9556 is a silicon CMOS circuit which provides parallel
input/output expansion for SMBus applications. The PCA9556
consists of an 8-bit input port register, 8-bit output port register, and
an SMBus interface. It has low current consumption and a high
impedance open drain output pin, I/O0.
The SMBus system master can reset the PCA9556 in the event of a
timeout by asserting a LOW on the reset input. The SMBus system
master can also invert the PCA9556 inputs by writing to the active
HIGH polarity inversion bits. Finally, the system master can enable
the PCA9556’s I/Os as either inputs or outputs by writing to the
configuration register.
The power-on reset puts the registers in their default state and
initializes the SMBus state machine. The RESET
pin causes the
same reset/initialization to occur without depowering the part.
The PCA9557 8-bit I
2
C SMBus I/O port with reset is the higher
performance pin-for-pin replacement for the PCA9556.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
su01045
SCL
SDA
A0
A1
A2
I/O0
I/O1
V
SS
V
DD
RESET
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER
SYMBOL FUNCTION
1 SCL Serial clock line
2 SDA Serial data line
3 A0 Address input 0
4 A1 Address input 1
5 A2 Address input 2
6 I/O0 I/O0 (open drain)
7 I/O1 I/O1
8 V
SS
Supply GROUND
9–14 I/O2–I/O7 I/O2 to I/O7
15 RESET External reset (active LOW)
16 V
DD
Supply voltage
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
16-Pin Plastic TSSOP –40 to +85 °C PCA9556PW SOT403-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I
2
C patent.
I
2
C is a trademark of Philips Semiconductors Corporation.
Philips Semiconductors Product data
PCA9556Octal SMBus and I
2
C registered interface
2002 Mar 28
3
BLOCK DIAGRAM
POWER-ON
RESET
INPUT
FILTER
SMBus
CONTROL
INPUT/
OUTPUT
PORTS
WRITE pulse
READ pulse
A0
A1
A2
SCL
SDA
V
DD
V
SS
8-BIT
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
SW00793
RESET
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
Figure 2. Block diagram
SYSTEM DIAGRAM
SW00794
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
6
7
9
10
11
12
13
14
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Input Port Polarity Inversion Configuration Output Port
RESET
SCL
SDA
A2
A1
A0
15
1
2
5
4
3
V
CC
= 16
GND = 8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
I
2
C/SMBus
Interface
logic
or
or
or
1.1 K
1.1 K
1.6 K
1.6 K
1.1 K
1.1 K
1.1 K
Figure 3. System diagram

PCA9556PW,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - I/O Expanders OCTAL SMBUS REG INTERFACE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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