LTC4444
10
4444fb
APPLICATIONS INFORMATION
At a particular switching frequency, the internal power loss
increases due to both AC currents required to charge and
discharge internal node capacitances and cross-conduc-
tion currents in the internal logic gates. The sum of the
quiescent current and internal switching current with no
load are shown in the Typical Performance Characteristics
plot of Switching Supply Current vs Input Frequency.
The gate charge losses are primarily due to the large AC
currents required to charge and discharge the capacitance
of the external MOSFETs during switching. For identical
pure capacitive loads C
LOAD
on TG and BG at switching
frequency f
IN
, the load losses would be:
P
CLOAD
= (C
LOAD
)(f)[(V
BOOST-TS
)
2
+ (V
CC
)
2
]
In a typical synchronous buck configuration, V
BOOST-TS
is equal to V
CC
– V
D
, where V
D
is the forward voltage
drop across the diode between V
CC
and BOOST. If this
drop is small relative to V
CC
, the load losses can be
approximated as:
P
CLOAD
= 2(C
LOAD
)(f
IN
)(V
CC
)
2
Unlike a pure capacitive load, a power MOSFET’s gate
capacitance seen by the driver output varies with its V
GS
voltage level during switching. A MOSFET’s capacitive load
power dissipation can be calculated using its gate charge,
QG. The QG value corresponding to the MOSFET’s V
GS
value (V
CC
in this case) can be readily obtained from the
manufacturer’s QG vs V
GS
curves. For identical MOSFETs
on TG and BG:
P
QG
= 2(V
CC
)(Q
G
)(f
IN
)
To avoid damage due to power dissipation, the LTC4444
includes a temperature monitor that will pull BG and TG
low if the junction temperature rises above 160°C. Normal
operation will resume when the junction temperature cools
to less than 135°C.
Bypassing and Grounding
The LTC4444 requires proper bypassing on the V
CC
and V
BOOST-TS
supplies due to its high speed switching
(nanoseconds) and large AC currents (Amperes). Careless
component placement and PCB trace routing may cause
excessive ringing.
To obtain the optimum performance from the LTC4444:
A. Mount the bypass capacitors as close as possible
between the V
CC
and GND pins and the BOOST and
TS pins. The leads should be shortened as much as
possible to reduce lead inductance.
B. Use a low inductance, low impedance ground plane
to reduce any ground drop and stray capacitance.
Remember that the LTC4444 switches greater than
3A peak currents and any significant ground drop will
degrade signal integrity.
C. Plan the power/ground routing carefully. Know where
the large load switching current is coming from and
going to. Maintain separate ground return paths for
the input pin and the output power stage.
D. Keep the copper trace between the driver output pin
and the load short and wide.
E. Be sure to solder the Exposed Pad on the back side of
the LTC4444 package to the board. Correctly soldered
to a 2500mm
2
double sided 1oz copper board, the
LTC4444 has a thermal resistance of approximately
40°C/W for the MS8E package. Failure to make good
thermal contact between the exposed back side and
the copper board will result in thermal resistances far
greater than 40°C/W.
