MAX7430EUB+T Datasheet MAX7430EUB+, MAX7428EVKIT, MAX7432EUD+T | P10-P12

MAX7428/MAX7430/MAX7432A

Standard Definition Video Reconstruction

Filters and Buffers

10 ______________________________________________________________________________________

CLEVEL: Clamp Level bit. A logic 0 selects a clamp

level of 1V while a logic 0 selects a clamp level of 1.5V

at the output.

[BOOST1, BOOST0]: High-Frequency Boost Control bits.

The adjust bits select the amount of high-frequency boost

for the filter. Table 2 defines four levels of adjustment.

OUTDISABLE: Output Disable bit. A logic 0 selects

normal operation while a logic 1 places the output in a

high-impedance state.

MAX7430 Control Register

Table 3 defines the structure of the MAX7430 16-bit con-

trol register programmed by MSPB. This register controls

the selection of IN_A or IN_B, selection of filter 1 or 2, filter

bypassing, clamp-level selection, high-frequency boost

control, and output disable. See Maxim’s Single Pin Bus

Interface (MSPB) section for detailed programming

instructions.

ABSEL_: Channel Select bit. A logic zero selects the

input at IN_B to be processed while a logic 1 selects

the input at IN_A to be processed.

BYPASS_: Filter Bypass Select bit. A logic 1 selects

the channel filter while a logic 0 bypasses the channel

filter.

CLEVEL_: Clamp Level bit. A logic 0 selects a channel

clamp level of 1V while a logic 0 selects a channel

clamp level of 1.5V at the output.

[BOOST1_, BOOST0_]: High-Frequency Boost Control

bits. The adjust bits select the amount of high-frequency

boost for the channel filter. Table 4 defines four levels of

adjustment.

OUTDISABLE_: Output Disable bit. A logic 0 selects

normal channel output operation while a logic 1 puts

the channel output in a high-impedance state.

MAX7432A Control Register

Table 5 defines the structure of the MAX7432A 24-bit

control register programmed by MSPB. This register

controls the selection of IN_A or IN_B, selection of filter

1, 2, or 3, filter bypassing, clamp-level selection, high-

frequency boost control, and output disable. See

Maxim’s Single-Pin Bus Interface (MSPB) section for

detailed programming instructions.

ABSEL_: Channel Select bit. A logic zero selects the

input at IN_B to be processed while a logic 1 selects

the input at IN_A to be processed.

BYPASS_: Filter Bypass Select bit. A logic 1 selects

the channel filter while a logic 0 bypasses the channel

filter.

CLEVEL_: Clamp Level bit. A logic 0 selects a channel

clamp level of 1V while a logic 0 selects a channel

clamp level of 1.5V at the output.

[BOOST1_, BOOST0_]: High-Frequency Boost Control

bits. The adjust bits select the amount of high-frequency

boost for the channel filter. Table 6 defines four levels of

adjustment.

OUTDISABLE_: Output Disable Bit. A logic 0 selects

normal channel output operation while a logic 1 puts

the channel output in high-impedance state.

(MSB)

NAME — ABSEL2

BYPASS2 CLEVEL2 BOOST1(2) BOOST0(2)

OUT

DISABLE2

—

DEFAULT 0 1 1 0 0 0 0 0

NAME — ABSEL1

BYPASS1 CLEVEL1 BOOST1(1) BOOST0(1)

OUT

DISABLE1

—

DEFAULT 0 1 1 0 0 0 0 0

FIRST BIT

(LSB)

Table 3. MAX7430 Control Register

BOOST1_ BOOST0_

RELATIVE HIGH

FREQUENCY BOOST

00 0

0 1 0.3dB to 0.5dB

1 0 0.6dB to 1.0dB

1 1 0.9dB to 1.5dB

Table 4. Boost Level Programming

MAX7428/MAX7430/MAX7432A

Standard Definition Video Reconstruction

Filters and Buffers

______________________________________________________________________________________ 11

Applications Information

Maxim’s Single Pin Bus (MSPB)

Serial Interface

The MSPB interface uses three pulses of different

widths to represent commands and data bits. Figure 4

shows the set of pulses that the single pin interface

uses to communicate with the device. A combination of

the one pulse (t

), zero pulse (t

), transaction pulse (t

and prompt pulse (t

), writes to, reads back from, and

sends broadcast data to the devices on the bus.

Note: The zero pulse and prompt pulse are the same.

Initialization pulses are significantly longer and are

used only on power-up or software reset.

Initializing the

MAX7428/MAX7430/MAX7432A

Initialization is performed only after power-up or software

reset. It assigns a unique address to each device on the

bus. The time constant of the capacitor connected to

EXT

in parallel with the 300kΩ resistor determines the

order in which the devices are initialized (address

assigned). The device with the largest time constant is

initialized first and so on, in descending order. Table 7

shows the “Initialize Wait” and “Initialize Time” pulse

widths needed for a specific capacitor value and toler-

ance. Program each device on the bus with this com-

mand sequence starting with the device with the biggest

capacitor. To reinitialize a device, cycle the power or use

a software reset. The following is the command

sequence and timing diagram (Figure 5) for initialization

as shown below. Chip ID is entered LSB first.

Note: If there is only one device on the bus, no initial-

ization is needed. Communicate to the device using the

broadcast command described on page 13.

(MSB)

NAME — ABSEL3

BYPASS3 CLEVEL3 BOOST1(3) BOOST0(3)

OUT

DISABLE3

—

DEFAULT 0 1 1 0 0 0 0 0

NAME — ABSEL2

BYPASS2 CLEVEL2 BOOST1(2) BOOST0(2)

OUT

DISABLE2

—

DEFAULT 0 1 1 0 0 0 0 0

NAME — ABSEL1

BYPASS1 CLEVEL1 BOOST1(1) BOOST0(1)

OUT

DISABLE1

—

DEFAULT 0 1 1 0 0 0 0 0

FIRST BIT

(LSB)

Table 5. MAX7432A Control Register

BOOST1_ BOOST0_

RELATIVE HIGH

FREQUENCY BOOST

00 0

0 1 0.3dB to 0.5dB

1 0 0.6dB to 1.0dB

1 1 0.9dB to 1.5dB

Table 6. Boost Level Programming

ZERO/PROMPT

PULSE

= t

= 5μs

= 30μs

ONE PULSE

TRANSACTION

PULSE

= 100μs

Figure 4. MSPB Interface Pulses

MAX7428/MAX7430/MAX7432A

Standard Definition Video Reconstruction

Filters and Buffers

12 ______________________________________________________________________________________

Programming the

MAX7428/MAX7430/MAX7432A

An address sequence precedes a write or read opera-

tion to determine with which device to communicate. If

the address transmitted in this mode matches with a

device’s address, the device and µP can initiate data

transfer. When entering the four address bits, ensure

that the LSB is entered first. The following is the com-

mand sequence and timing diagram (Figure 6) for an

address sequence.

Use a write sequence to load data into the data register

of the device. It must follow an address sequence.

Transmit a minimum of eight data bits for the MAX7428,

16 data bits for the MAX7430, or 24 data bits for the

MAX7432A to make this transaction valid starting with

the LSB first. The last 8/16/24 data bits are used if more

than 8/16/24 bits are loaded into the register. The fol-

lowing is the command sequence and timing diagram

(Figure 7) for a write sequence.

During the read sequence, the µP sends a prompt

pulse causing the device to output the data word LSB

first. Similar to the write transaction, the read transac-

tion must be preceded by an address sequence. If

more than 8 prompts (MAX7428), 16 prompts

(MAX7430), or 24 prompts (MAX7432A) are available,

the device outputs the same data starting with the LSB

again. The following is the command sequence and

timing diagram (Figure 8) for a read sequence.

Write Command Sequence:

T001

Data ≥ 8-bits (MAX7428,

See Table 1)

Data ≥ 16-bits (MAX7430,

See Table 3)

Data ≥ 24-bits (MAX7432A,

See Table 5)

T111

Address Command Sequence:

T010 Address = 4-bits T111

Initialization Command Sequence:

Initialize wait T011

Initialize Time

Address ID = 4-bits T111

INITIALIZING TIME PERIOD (ms)

WITH R

REXT

= 300kΩ (t

INT

)

CAPACITOR VALUE (nF)

INITIALIZING WAIT PERIOD

(ms) (t

INTWAIT

)

MIN TYP MAX

1000 20.000 162 (136.8) 171 (144) 179 (151.2)

680 13.600 112 118 123

470 9.400 52.6 (44.1) 55.4 (46.4) 58.2 (48.72)

220 4.400 35.90 37.80 39.70

150 3.000 23.90 (13.7) 25.20 (14.4) 26.50 (15.1)

100 2.000 16.25 17.10 17.95

68 1.360 11.21 (4.4) 11.80 (4.64) 12.39 (4.9)

47 0.940 5.26 5.54 5.82

22 0.440 3.59 3.78 3.97

15 0.300 2.39 2.52 2.65

10 0.200 1.625 (1.37) 1.710 (1.44) 1.795 (1.51)

6.8 0.136 1.121 1.180 1.239

4.7 0.094 0.526 (0.441) 0.554 (0.464) 0.582 (0.487)

2.2 0.044 0.359 0.378 0.397

1.5 0.030 0.239 0.252 0.265

1 0.020 0.162 (0.137) 0.171 (0.144) 0.179 (0.151)

Table 7. Initialization Capacitor Values and Pulse Widths

(CREXT = ±10% Tolerance, RREXT = ±1% Tolerance)

Note: ( ) Indicates the time periods associated with 20% capacitors. This limits the maximum number of devices on the bus to seven.

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MAX7430EUB+T

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Multimedia ICs Video ICs Standard Def Video Reconstruction Filt

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