LT1800
12
1800fa
APPLICATIONS INFORMATION
Circuit Description
The LT1800 has an input and output signal range that cov-
ers from the negative power supply to the positive power
supply. Figure 1 depicts a simplifi ed schematic of the
amplifi er. The input stage is comprised of two differential
amplifi ers, a PNP stage Q1/Q2 and an NPN stage Q3/Q4
that are active over the different ranges of common mode
input voltage. The PNP differential pair is active between the
negative supply to approximately 1.2V below the positive
supply. As the input voltage moves closer toward the posi-
tive supply, the transistor Q5 will steer the tail current I
1
to
the current mirror Q6/Q7, activating the NPN differential
pair and the PNP pair becomes inactive for the rest of the
input common mode range up to the positive supply. Also
at the input stage, devices Q17 to Q19 act to cancel the bias
current of the PNP input pair. When Q1-Q2 are active, the
current in Q16 is controlled to be the same as the current
in Q1-Q2, thus the base current of Q16 is nominally equal
to the base current of the input devices. The base current
of Q16 is then mirrored by devices Q17-Q19 to cancel the
base current of the input devices Q1-Q2.
A pair of complementary common emitter stages Q14/Q15
that enable the output to swing from rail to rail constructs
the output stage. The capacitors C2 and C3 form the lo-
cal feedback loops that lower the output impedance at
high frequency. These devices are fabricated on Linear
Technology’s proprietary high speed complementary
bipolar process.
Power Dissipation
The LT1800 amplifi er is offered in a small package, SOT-23,
which has a thermal resistance of 250°C/W, θ
JA
. So there is
a need to ensure that the die’s junction temperature should
not exceed 150°C. Junction temperature T
J
is calculated
from the ambient temperature T
A
, power dissipation P
D
and thermal resistance θ
JA
:
T
J
= T
A
+ (P
D
• θ
JA
)
The power dissipation in the IC is the function of the sup-
ply voltage, output voltage and the load resistance. For
a given supply voltage, the worst-case power dissipation
P
DMAX
occurs at the maximum supply current and the
Q4
Q18Q17
Q16
Q6
Q3
Q7
Q10
Q1
Q13 Q15
OUT
Q2
Q11
Q12
Q9
Q5 V
BIAS
I
1
D2
D1
D5
D4
D3
D6
D7
D8
ESDD2ESDD1
+IN
–IN
V
–
ESDD3ESDD4
V
+
V
+
V
–
Q8
R2R1
R3 R4 R5
Q14
1800 F01
+
I
2
+
I
3
C2
C
C
V
–
+
C1
BUFFER
AND
OUTPUT BIAS
V
+
V
–
Q19
Figure 1. LT1800 Simplifi ed Schematic Diagram
