11
FN8114.2
August 25, 2008
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to the
Register during a write operation. This bit is a volatile latch
that powers up in the LOW (disabled) state. While the WEL
bit is LOW, writes to any address, including any control
registers will be ignored (no acknowledge will be issued after
the Data Byte). The WEL bit is set by writing a “1” to the
WEL bit and zeroes to the other bits of the control register.
Once set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits of the
control register) or until the part powers up again. Writes to
the WEL bit do not cause a high voltage write cycle, so the
device is ready for the next operation immediately after the
stop condition.
PUP1, PUP0: Power-Up Bits (Nonvolatile)
The Power-up bits, PUP1 and PUP0, determine the t
PURST
time delay. The nominal power-up times are shown in Table 2.
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the Watchdog
Timer. The options are shown in Table 3.
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and trickle
registers requires the following steps:
• Write a 02H to the Control Register to set the Write Enable
Latch (WEL). This is a volatile operation, so there is no
delay after the write (operation preceded by a start and
ended with a stop).
• Write a 06H to the Control Register to set the Register
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required
(operation proceeded by a start and ended with a stop).
• Write one byte value to the Control Register that has all
the control bits set to the desired state. The Control
register can be represented as qxys 001r in binary, where
xy are the WD bits, s is the BP bit and qr are the power-up
bits. This operation proceeded by a start and ended with a
stop bit. Since this is a nonvolatile write cycle it will take up
to 10ms (max.) to complete. The RWEL bit is reset by this
cycle and the sequence must be repeated to change the
nonvolatile bits again. If bit 2 is set to ‘1’ in this third step
(qxys 011r) then the RWEL bit is set, but the WD1, WD0,
PUP1, PUP0, and BP bits remain unchanged. Writing a
second byte to the control register is not allowed. Doing so
aborts the write operation and returns a NACK.
• A read operation occurring between any of the previous
operations will not interrupt the register write operation.
• The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, or power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consisting of
[02H, 06H, 02H] will reset all of the nonvolatile bits in the
Control Register to 0. A sequence of [02H, 06H, 06H] will
leave the nonvolatile bits unchanged and the RWEL bit
remains set.
Note: t
PURST
is set to 200ms as factory default. Watchdog
Timer bits are shipped disabled.
Fault Detection Register (FDR)
The Fault Detection Register provides the user the status of
what causes the system reset active. The Manual Reset
Fail, Watchdog Timer Fail and Three Low Voltage Fail bits
are volatile.
The FDR is accessed with a special preamble in the slave
byte (1011) and is located at address 0FFh. It can only be
modified by performing a byte write operation directly to the
address of the register and only one data byte is allowed for
each register write operation.
There is no need to set the WEL or RWEL in the control
register to access this FDR.
At power-up, the FDR is defaulted to all “0”. The system
needs to initialize this register to all “1” before the actual
monitoring can take place. In the event of any one of the
monitored sources fail, the corresponding bit in the register
will change from a “1” to a “0” to indicate the failure. At this
moment, the system should perform a read to the register
and note the cause of the reset. After reading the register,
the system should reset the register back to all “1” again.
The state of the FDR can be read at any time by performing
a random read at address 0FFh, using the special preamble.
The FDR can be read by performing a random read at 0FFh
address of the register at any time. Only one byte of data is
read by the register read operation.
TABLE 2. NOMINAL POWER-UP TIMES
PUP1 PUP0 POWER-ON RESET DELAY (t
PURST
)
0 0 50ms
0 1 200ms (factory setting)
1 0 400ms
1 1 800ms
TABLE 3. WATCHDOG TIMER OPTIONS
WD1 WD0 WATCHDOG TIME OUT PERIOD
0 0 1.4s
0 1 200ms
1 0 25ms
1 1 Disabled (factory setting)
7 6543210
LV1F LV2F LV3F WDF MRF 0 0 0
X40030, X40031, X40034, X40035
