R1LP5256E Series
R10DS0070EJ0100 Rev.1.00 Page 12 of
13
2011.04.13
Low Vcc Data Retention Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions
*2
V
CC
for data retention V
DR
2.0 - 5.5 V
Vin ≥ 0V
CS# ≥ Vcc-0.2V
- 1
*1
2 μA ~+25°C
- - 3 μA ~+40°C
- - 8 μA ~+70°C
Data retention current I
CCDR
- - 10 μA ~+85°C
Vcc=3.0V, Vin ≥ 0V,
CS# ≥ Vcc-0.2V
Chip deselect to data retention time t
CDR
0 - - ns
Operation recovery time t
R
5 - - ms
See retention waveform.
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS# controls address buffer, WE# buffer, OE# buffer and Din buffer. If CS# controls data retention mode, Vin
levels (address, WE#, OE#, DQ) can be in the high impedance state.
