OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

83940DYILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
DATA SHEET
ICS83940DYI REVISION C May 19, 2016 1 ©2016 Integrated Device Technology, Inc.
Low Skew, 1-to18
LVPECL-to-LVCMOS/LVTTL Fanout Buffer
ICS83940DI
General Description
The ICS83940DI is a low skew, 1-to-18 LVPECL- to-LVCMOS/LVTTL
Fanout Buffer. The ICS83940DI has two selectable clock inputs. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The
low impedance LVCMOS/LVTTL outputs are designed to drive 50
series or parallel terminated transmission lines.
The ICS83940DI is characterized at full 3.3V and 2.5V or mixed 3.3V
core, 2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the ICS83940DI ideal for
those clock distribution applications demanding well defined
performance and repeatability.
Block Diagram
Features
• Eighteen LVCMOS/LVTTL outputs
• Selectable LVCMOS_CLK or LVPECL clock inputs
• PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
• LVCMOS_CLK supports the following input types: LVCMOS or
LVTTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Operating supply modes:
• Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
• For functional replacement part for 83940DKILF use 87016i
Pin Assignments
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
CLK_SEL
PCLK
nPCLK
LVCMOS_CLK
0
1
18
Q0:Q17
Pulldown
Pulldown
Pulldown
Pullup/Pulldown
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
VDDO
Q6
Q7
Q8
V
DD
Q9
Q10
Q11
GND
Q17
Q16
Q15
GND
Q14
Q13
Q12
V
DDO
Q1
Q2
V
DDO
Q3
Q4
Q5
GND
Q0
ICS83940DI
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q6
Q7
Q8
V
DD
Q9
Q10
Q11
GND
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
VDDO
GND
Q5
Q4
Q3
V
DDO
Q2
Q1
Q0
Q17
Q16
Q14
Q15
GND
Q13
Q12
V
DDO
ICS83940DI
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 (83940DKILF)
ICS83940DYI REVISION C May 19, 2016 2 ©2016 Integrated Device Technology, Inc.
ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2, 12, 17, 25 GND Power Power supply ground.
3 LVCMOS_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
4 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects PCLK, nPCLK inputs.
LVCMOS / LVTTL interface levels.
5 PCLK Input Pulldown Non-inverting differential LVPECL clock input.
6nPCLKInput
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
7, 21 V
DD
Power Power supply pin.
8, 16, 29 V
DDO
Power Output supply pins.
9, 10, 11,
13, 14, 15,
18, 19, 20,
22, 23, 24,
26, 27, 28,
30, 31, 32
Q17, Q16, Q15,
Q14, Q13, Q12,
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
C
PD
Power Dissipation Capacitance
(per output)
6pF
R
OUT
Output Impedance 18 28
ICS83940DYI REVISION C May 19, 2016 3 ©2016 Integrated Device Technology, Inc.
ICS83940DI Data Sheet LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Function Tables
Table 3A. Clock Select Function Table
Table 3B. Clock Input Function Table
NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels.
Control Input Clock
CLK_SEL PCLK, nPCLK LVCMOS_CLK
0 Selected De-selected
1 De-selected Selected
Inputs Outputs
Input to Output Mode PolarityCLK_SEL LVCMOS_CLK PCLK nPCLK Q[0:17]
0–01LOWDifferential to Single-EndedNon-Inverting
0–10HIGHDifferential to Single-EndedNon-Inverting
0 – 0 Biased; NOTE 1 LOW Single-Ended to Single-Ended Non-Inverting
0 – 1 Biased; NOTE 1 HIGH Single-Ended to Single-Ended Non-Inverting
0 – Biased; NOTE 1 0 HIGH Single-Ended to Single-Ended Inverting
0 – Biased; NOTE 1 1 LOW Single-Ended to Single-Ended Inverting
10––LOWSingle-Ended to Single-EndedNon-Inverting
11––HIGHSingle-Ended to Single-EndedNon-Inverting
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

83940DYILF

Mfr. #:
Buy 83940DYILF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 18 LVCMOS OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet