2
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE
Device Instruction Data Floating Bus
Name Cache Cache Point Options
R3051 4kB 2kB Software Emulation Mux’ed A/D
R3052 8kB 2kB Software Emulation Mux’ed A/D
R3071 16kB 4kB On-chip Hardware 1/2 frequency bus option
R3081 or 8kB or 8kB
R3041 2kB 512B Software Emulation 8-, 16-, and 32-bit port width support
Programmable timing support
2905 tbl 01
INTRODUCTION
The IDT RISController family is a series of high-perfor-
mance 32-bit microprocessors featuring a high-level of inte-
gration, and targeted to high-performance but cost sensitive
embedded processing applications. The RISController family
is designed to bring the high-performance inherent in the
MIPS RISC architecture into low-cost, simplified, power sen-
sitive applications.
Thus, functional units have been integrated onto the CPU
core in order to reduce the total system cost, rather than to
increase the inherent performance of the integer engine.
Nevertheless, the RISController family is able to offer 35MIPS
of integer performance at 40MHz without requiring external
SRAM or caches.
Further, the RISController family brings dramatic power
reduction to these embedded applications, allowing the use of
low-cost packaging. Thus, the RISController family allows
customer applications to bring maximum performance at
minimum cost.
The R3041 extends the range of price/performance achiev-
Table 1. Pin-Compatible RISController Family
Figure 2. RISController Family 5-Stage Pipeline
CPU Core
The CPU core is a full 32-bit RISC integer execution
engine, capable of sustaining close to a single cycle execution
rate. The CPU core contains a five stage pipeline, and 32
orthogonal 32-bit registers. The RISController family imple-
ments the MIPS-I Instruction Set Architecture (ISA). In fact,
the execution engine of the R3041 is the same as the
execution engine of the R3000A. Thus, the R3041 is binary
compatible with those CPU engines, as well as compatible
with other members of the RISController family.
able with the RISController family, by dramatically lowering
the cost of using the MIPS architecture. The R3041 is de-
signed to achieve minimal system and components cost, yet
maintain the high-performance inherent in the MIPS architec-
ture. The R3041 also maintains pin and software compatibility
with the RISController and R3081.
The RISController family offers a variety of price/perfor-
mance features in a pin-compatible, software compatible
family. Table 1 provides an overview of the current members
of the RISController family. Note that the R3051, R3052, and
R3081 are also available in pin-compatible versions that
include a full-function memory management unit, including
64-entry TLB. The R3051/2 and R3081 are described in
separate manuals and data sheets.
Figure 1 shows a block level representation of the func-
tional units within the R3041. The R3041 can be viewed as the
embodiment of a discrete solution built around the R3000A.
By integrating this functionality on a single chip, dramatic cost
and power reductions are achieved.
An overview of these blocks is presented here, followed
with detailed information on each block.
IF
Current
CPU
Cycle
I#1 ALURD MEM WB
IFI#2 ALURD MEM WB
IFI#3 ALURD MEM WB
IFI#4 ALURD MEM WB
IFI#5 ALURD MEM WB
2905 drw 02
The execution engine of the RISController family uses a
five-stage pipeline to achieve close to single cycle execution.
A new instruction can be started in every clock cycle; the
execution engine actually processes five instructions concur-
rently (in various pipeline stages). The five parts of the pipeline
are the Instruction Fetch, Read register, ALU execution,
Memory, and Write Back stages. Figure 2 shows the
concurrency achieved by the RISController family pipeline.
