AD7730LBRZ-REEL Datasheet AD7730BRUZ, AD7730BNZ, AD7730BRZ | P16-P18

AD7730/AD7730L

–16–

MD2 MD1 MD0 Operating Mode

0 0 0 Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7730 is not

processing any new samples or data. Placing the part in this mode is equivalent to exerting the SYNC

input pin. However, exerting the SYNC pin does not actually force these mode bits to 0, 0, 0. The part

returns to this mode after a calibration or after a conversion in Single Conversion Mode. This is the

default condition of these bits after Power-On/Reset.

0 0 1 Continuous Conversion Mode. In this mode, the AD7730 is continuously processing data and providing

conversion results to the Data Register at the programmed output update rate (as determined by the

Filter Register). For most applications, this would be the normal operating mode of the AD7730.

0 1 0 Single Conversion Mode. In this mode, the AD7730 performs a single conversion, updates the Data

on the AD7730 in this mode will not be provided until the full settling time of the filter has elapsed.

0 1 1 Power-Down (Standby) Mode. In this mode, the AD7730 goes into its power-down or standby state.

Placing the part in this mode is equivalent to exerting the STANDBY input pin. However, exerting

STANDBY does not actually force these mode bits to 0, 1, 1.

1 0 0 Zero-Scale Self-Calibration Mode. This activates zero-scale self-calibration on the channel selected by

CH1 and CH0 of the Mode Register. This zero-scale self-calibration is performed at the selected gain on

internally shorted (zeroed) inputs. When this zero-scale self-calibration is complete, the part updates the

contents of the appropriate Offset Calibration Register and returns to Sync Mode with MD2, MD1 and

MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and return low

when this zero-scale self-calibration is complete to indicate that the part is back in Sync Mode and ready

for further operations.

1 0 1 Full-Scale Self-Calibration Mode. This activates full-scale self-calibration on the channel selected by

CH1 and CH0 of the Mode Register. This full-scale self-calibration is performed at the selected gain on

an internally-generated full-scale signal. When this full-scale self-calibration is complete, the part updates

the contents of the appropriate Gain Calibration Register and Offset Calibration Register and returns to

Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when

calibration is initiated and return low when this full-scale self-calibration is complete to indicate that the

part is back in Sync Mode and ready for further operations.

1 1 0 Zero-Scale System Calibration Mode. This activates zero scale system calibration on the channel selected

by CH1 and CH0 of the Mode Register. Calibration is performed at the selected gain on the input volt-

age provided at the analog input during this calibration sequence. This input voltage should remain

stable for the duration of the calibration. When this zero-scale system calibration is complete, the part

updates the contents of the appropriate Offset Calibration Register and returns to Sync Mode with MD2,

MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and

return low when this zero-scale calibration is complete to indicate that the part is back in Sync Mode and

ready for further operations.

1 1 1 Full-Scale System Calibration Mode. This activates full-scale system calibration on the selected input

channel. Calibration is performed at the selected gain on the input voltage provided at the analog input

during this calibration sequence. This input voltage should remain stable for the duration of the calibra-

tion. When this full-scale system calibration is complete, the part updates the contents of the appropriate

Gain Calibration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0.

The RDY output and bit go high when calibration is initiated and return low when this full-scale calibra-

tion is complete to indicate that the part is back in Sync Mode and ready for further operations.

REV. B

AD7730/AD7730L

–17–

Bit Bit

Location Mnemonic Description

MR12 B/U Bipolar/Unipolar Bit. A 0 in this bit selects bipolar operation and the output coding is 00. . . 000 for

negative full-scale input, 10 . . . 000 for zero input, and 11 . . . 111 for positive full-scale input. A 1 in

this bit selects unipolar operation and the output coding is 00 . . . 000 for zero input and 11 . . . 111 for

positive full-scale input.

MR11 DEN Digital Output Enable Bit. With this bit at 1, the AIN2(+)/D1 and AIN2(–)/D0 pins assume their

digital output functions and the output drivers connected to these pins are enabled. In this mode, the

user effectively has two port bits which can be programmed over the serial interface.

MR10–MR9 D1–D0 Digital Output Bits. These bits determine the digital outputs on the AIN2(+)/D1 and AIN2(–)/D0 pins,

respectively, when the DEN bit is a 1. For example, a 1 written to the D1 bit of the Mode Register

(with the DEN bit also a 1) will put a logic 1 on the AIN2(+)/D1 pin. This logic 1 will remain on this

pin until a 0 is written to the D1 bit (in which case the AIN2(+)/D1 pin goes to a logic 0) or the digital

output function is disabled by writing a 0 to the DEN bit.

MR8 WL Data Word Length Bit. This bit determines the word length of the Data Register. A 0 in this bit selects

16-bit word length when reading from the data register (i.e., RDY returns high after 16 serial clock

cycles in the read operation). A 1 in this bit selects 24-bit word length for the Data Register.

MR7 HIREF High Reference Bit. This bit should be set in accordance with the reference voltage which is being used

on the part. If the reference voltage is 5 V, the HIREF bit should be set to 1. If the reference voltage is

2.5 V, the HIREF bit should be set to a 0. With the HIREF bit set correctly for the appropriate applied

reference voltage, the input ranges are 0 mV to +10 mV, +20 mV, +40 mV and +80 mV for unipolar

operation and ± 10 mV, ± 20 mV, ± 40 mV and ±80 mV for bipolar operation.

It is possible for a user with a 2.5 V reference to set the HIREF bit to a 1. In this case, the part is oper-

ating with a 2.5 V reference but assumes it has a 5 V reference. As a result, the input ranges on the part

become 0 to +5 mV, +10 mV, +20 mV and +40 mV for unipolar operation and ± 5 mV, ± 10 mV,

± 20 mV and ±40 mV for bipolar operation. However, the output noise from the part (in nV) will re-

main unchanged so the resolution of the part (in counts) will halve.

MR6 ZERO A zero must be written to this bit to ensure correct operation of the AD7730.

MR5–MR4 RN1–RN0 Input Range Bits. These bits determine the analog input range for the selected analog input. The dif-

ferent input ranges are outlined in Table XII. The table is valid for a reference voltage of 5 V with the

HIREF bit at 1, or for a reference voltage of 2.5 V with the HIREF bit at a logic 0.

Table XII. Input Range Selection

Input Range

RN1 RN0 B/U Bit = 0 B/U Bit = 1

0 0 –10 mV to +10 mV 0 mV to +10 mV

0 1 –20 mV to +20 mV 0 mV to +20 mV

1 0 –40 mV to +40 mV 0 mV to +40 mV

1 1 –80 mV to +80 mV 0 mV to +80 mV Power-On/Reset Default

Note that the input range given in the above table is the range that appears at the input of the PGA

after the DAC offset value has been applied. If the DAC adjusts out no offset (DAC Register is 0010

0000), then this is also the input voltage range at the analog input pins. If, for example, the DAC sub-

tracts out 50 mV of offset and the part is being operated in bipolar mode with RN1 and RN0 at 0, 0,

the actual input voltage range at the analog input is +40 mV to +60 mV.

MR3 CLKDIS Master Clock Disable Bit. A 1 in the bit disables the master clock from appearing at the MCLK OUT

pin. When disabled, the MCLK OUT pin is forced low. It allows the user the flexibility of using the

MCLK OUT as a clock source for other devices in the system or of turning off the MCLK OUT as a

power saving feature. When using an external master clock at the MCLK IN pin, the AD7730 contin-

ues to have internal clocks and will convert normally with the CLKDIS bit active. When using a crystal

oscillator or ceramic resonator across the MCLK IN and MCLK OUT pins, the AD7730 clock is

stopped and no conversions take place when the CLKDIS bit is active.

REV. B

AD7730/AD7730L

–18–

Bit Bit

Location Mnemonic Description

MR2 BO Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout currents

connect to the selected analog input pair, one source current to the AIN(+) input and one sink current to

the AIN(–) input. A 0 in this bit turns off the on-chip burnout currents.

MR1–MR0 CH1–CH0 Channel Selection Bits. These bits select the analog input channel to be converted or calibrated as

outlined in Table XIII. With CH1 at 1 and CH0 at 0, the part looks at the AIN1(–) input internally

shorted to itself. This can be used as a test method to evaluate the noise performance of the part with

no external noise sources. In this mode, the AIN1(–) input should be connected to an external voltage

within the allowable common-mode range of the part. The Offset and Gain Calibration Registers on

the part are paired. There are three pairs of calibration registers labelled Register Pair 0 through Regis-

ter Pair 2. These are assigned to the input channel pairs as outlined in Table XIII.

Table XIII. Channel Selection

Input Channel Pair

CH1 CH0 Positive Input Negative Input Calibration Register Pair

0 0 AIN1(+) AIN1(–) Register Pair 0

0 1 AIN2(+) AIN2(–) Register Pair 1

1 0 AIN1(–) AIN1(–) Register Pair 0

1 1 AIN1(–) AIN2(–) Register Pair 2

Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 200010 Hex

The Filter Register is a 24-bit register from which data can be read or to which data can be written. This register determines the

amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode and the delay

associated with chopping the inputs. Table XIV outlines the bit designations for the Filter Register. FR0 through FR23 indicate the

bit location, FR denoting the bits are in the Filter Register. FR23 denotes the first bit of the data stream. The number in brackets

indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7730 and

Figure 6 shows a flowchart for writing to the registers on the part.

Table XIV. Filter Register

FR23 FR22 FR21 FR20 FR19 FR18 FR17 FR16

SF11 (0) SF10 (0) SF9 (1) SF8 (0) SF7 (0) SF6 (0) SF5 (0) SF4 (0)

FR15 FR14 FR13 FR12 FR11 FR10 FR9 FR8

SF3 (0) SF2 (0) SF1 (0) SF0 (0) ZERO (0) ZERO (0) SKIP (0) FAST (0)

FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0

ZERO (0) ZERO (0) AC (0) CHP (1) DL3 (0) DL2 (0) DL1 (0) DL0 (0)

Bit Bit

Location Mnemonic Description

FR23–FR12 SF11–SF0 Sinc

Filter Selection Bits. The AD7730 contains two filters: a sinc

filter and an FIR filter. The 12 bits

programmed to SF11 through SF0 set the amount of averaging the sinc

filter performs. As a result,

the number programmed to these 12 bits affects the –3 dB frequency and output update rate from the

part (see Filter Architecture section). The allowable range for SF words depends on whether the part

is operated with CHOP on or off and SKIP on or off. Table XV outlines the SF ranges for different

setups. All output update rates will be one-half those quoted in Table XV for the AD7730L operating

with a 2.4576 MHz clock.

REV. B

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P53

AD7730LBRZ-REEL

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Buy AD7730LBRZ-REEL

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 24-Bit Low Pwr

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AD7730LBRZ-REEL

AD7730LBRZ-REEL

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