X9418WV24IT1 Datasheet X9418WS24IZ, X9418YV24Z, X9418YS24IZ | P1-P3

X9418

Low Noise/Low Power/2-Wire Bus

Dual Digitally Controlled Potentiometers

(XDCP™)

FEATURES

• Two potentiometers in one package

• 2-wire serial interface

• Register oriented format

—Direct Read/Write/Transfer Wiper Position

—Store as many as Four Positions per

Potentiometer

• Power supplies

—V

= 2.7V to 5.5V

—V+ = 2.7V to 5.5V

—V– = -2.7V to -5.5V

• Low power CMOS

—Standby current < 1µA

—Ideal for Battery Operated Applications

• High reliability

—Endurance–100,000 Data Changes per Bit per

—Register Data Retention–100 years

• 8-bytes of nonvolatile memory

•2.5k, 10k resistor array

• Resolution: 64 taps each potentiometer

• 24-pin plastic DIP, 24-lead TSSOP and 24-lead

SOIC packages

• Pb-Free plus anneal available (RoHS compliant)

DESCRIPTION

The X9418 integrates two digitally controlled

potentiometers (XDCP) on a monolithic CMOS

integrated microcircuit.

The digitally controlled potentiometer is implemented

using 63 resistive elements in a series array. Between

each element are tap points connected to the wiper

terminal through switches. The position of the wiper on

the array is controlled by the user through the 2-wire

bus interface. Each potentiometer has associated with

it a volatile Wiper Counter Register (WCR) and 4

nonvolatile Data Registers (DR0:DR3) that can be

directly written to and read by the user. The contents

of the WCR controls the position of the wiper on the

resistor array through the switches. Power up recalls

the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal

potentiometer or as a two-terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

BLOCK DIAGRAM

R0 R1

R2 R3

Resistor

Array

XDCP1

R0 R1

R2 R3

Wiper

Counter

(WCR)

Interface

and

Control

Circuitry

SCL

SDA

Data

Wiper

Counter

(WCR)

V+

V-

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Data Sheet FN8194.3October 12, 2006

FN8194.3

October 12, 2006

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the

X9418.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into

and out of the device. It is an open drain output and

may be wire-ORed with any number of open drain or

open collector outputs. An open drain output requires

the use of a pull-up resistor. For selecting typical

values, refer to the guidelines for calculating typical

values on the bus pull-up resistors graph.

Device Address (A

- A

)

The Address inputs are used to set the least

significant 4 bits of the 8-bit slave address. A match in

the slave address serial data stream must be made

with the Address input in order to initiate

communication with the X9418. A maximum of 16

devices may occupy the 2-wire serial bus.

Potentiometer Pins

- V

), V

- V

)

The V

and V

inputs are equivalent to the

terminal connections on either end of a mechanical

potentiometer.

- V

)

The wiper outputs are equivalent to the wiper output of

a mechanical potentiometer.

Hardware Write Protect Input (WP

)

The WP

pin when low prevents nonvolatile writes to

the Data Registers.

Analog Supplies V+, V-

The Analog Supplies V+, V- are the supply voltages

for the XDCP analog section.

Ordering Information

PART NUMBER PART MARKING

LIMITS

(V)

POTENTIOMET

ORGANIZATION

(k)

TEMPERATU

RE RANGE

(°C) PACKAGE PKG. DWG. #

X9418WV24* X9418WV 5 ±10% 10 0 to +70 24 Ld TSSOP (4.4MM) MDP0044

X9418WV24Z* (Note) X9418WV Z 0 to +70 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044

X9418WP24I-2.7 X9418WP G 2.7 to 5.5 10 -40 to +85 24 Ld PDIP E24.6

X9418WS24I-2.7 X9418WS G -40 to +85 24 Ld SOIC (300MIL) M24.3

X9418WS24IZ-2.7 (Note) X9418WS ZG -40 to +85 24 Ld SOIC (300MIL) (Pb-free) M24.3

X9418WV24-2.7* X9418WV F 0 to +70 24 Ld TSSOP (4.4MM) MDP0044

X9418WV24Z-2.7* (Note) X9418WV ZF 0 to +70 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044

X9418WV24I-2.7 X9418WV G -40 to +85 24 Ld TSSOP (4.4MM) MDP0044

X9418WV24IZ-2.7 (Note) X9418WV ZG -40 to +85 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044

X9418YS24-2.7 X9418YS F 2.5 0 to +70 24 Ld SOIC (300MIL) M24.3

X9418YS24Z-2.7 (Note) X9418YS ZF 0 to +70 24 Ld SOIC (300MIL) (Pb-free) M24.3

X9418YS24I-2.7 X9418YS G -40 to +85 24 Ld SOIC (300MIL) M24.3

X9418YS24IZ-2.7 (Note) X9418YS ZG -40 to +85 24 Ld SOIC (300MIL) (Pb-free) M24.3

X9418YV24I-2.7* X9418YV G -40 to +85 24 Ld TSSOP (4.4MM) MDP0044

X9418YV24IZ-2.7* (Note) X9418YV ZG -40 to +85 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

X9418

FN8194.3

October 12, 2006

PIN CONFIGURATION

PIN NAMES

PRINCIPLES OF OPERATION

The X9418 is a highly integrated microcircuit

incorporating two resistor arrays and their associated

registers and counters and the serial interface logic

providing direct communication between the host and

the XDCP potentiometers.

Serial Interface

The X9418 supports a bidirectional bus oriented

protocol. The protocol defines any device that sends

data onto the bus as a transmitter and the receiving

device as the receiver. The device controlling the

transfer is a master and the device being controlled is

the slave. The master will always initiate data transfers

and provide the clock for both transmit and receive

operations. Therefore, the X9418 will be considered a

slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW periods (t

LOW

). SDA state changes during

SCL HIGH are reserved for indicating start and stop

conditions.

Start Condition

All commands to the X9418 are preceded by the start

condition, which is a HIGH to LOW transition of SDA

while SCL is HIGH (t

HIGH

). The X9418 continuously

monitors the SDA and SCL lines for the start condition

and will not respond to any command until this

condition is met.

Stop Condition

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide

a positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

bits. The master generates a ninth clock cycle and

during this period the receiver pulls the SDA line LOW

to acknowledge that it successfully received the eight

bits of data.

Symbol Description

SCL Serial Clock

SDA Serial Data

A0 - A3 Device Address

- V

Potentiometer Pins

(terminal equivalent)

Potentiometer Pins

(wiper equivalent)

Hardware Write Protection

V+,V- Analog Supplies

System Supply Voltage

System Ground

NC No Connection

SDA

V+

SCL

DIP/SOIC

X9418

V-

SDA

V+

X9418

V-

SCL

TSSOP

X9418

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

X9418WV24IT1

Mfr. #:

Buy X9418WV24IT1

Manufacturer:

Renesas / Intersil

Description:

IC XDCP DUAL 64-TAP 10K 24-TSSOP

Lifecycle:

New from this manufacturer.

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X9418WV24IT1

X9418WV24IT1

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