MAX4536/MAX4537/MAX4538
Quad, Low-Voltage,
SPST Analog Switches with Enable
_______________________________________________________________________________________ 7
0
-100
0.1 10 10001 100
FREQUENCY RESPONSE
-80
MAX4536/7/8 TOC-10
FREQUENCY (MHz)
LOSS (dB)
PHASE (DEGREES)
-60
-40
-20
-10
-90
-70
-50
-30
50
-50
-30
-10
10
30
40
-40
-20
0
20
-
ON-PHASE
ON-RESPONSE
OFF-ISOLATION
2.5
0
0123 67 10
LOGIC-LEVEL THRESHOLD 
vs. POSITIVE SUPPLY VOLTAGE
1.5
MAX4536/37/38 TOC-11
SUPPLY VOLTAGE (V)
LOGIC-LEVEL THRESHOLD (V)
45 89
2.0
0.5
1.0
100
0.01
10 1k 100k100 10k
TOTAL HARMONIC
DISTORTION vs. FREQUENCY
0.1
MAX4536/7/8 TOC-12
FREQUENCY (Hz)
THD (%)
10
1
V+ = 5V
V- = -5V
5Vp-p SIGNAL
600 IN AND OUT
_____________________________Typical Operating Characteristics (continued)
(V+ = +5V, V- = -5V GND = 0V, T
A
= +25°C, unless otherwise noted.)
______________________________________________________________Pin Description
Negative Analog Supply-Voltage Input. Connect V- to GND for single-supply operation.V-9
Positive Analog and Digital Supply-Voltage Input. Internally connected to substrate.V+16
Ground. Connect to digital ground. (Analog signals have no ground reference;
they are limited to V+ and V-.)
GND8
Disable Logic Input. Connect logic high to EN to disable (open) all switches.EN
7
PIN
Analog Switch Normally Open* or Normally Closed* Terminals (see
Truth Tables
)
NO1–NO4,
or
NC1–NC4
2, 3, 11, 12
Analog Switch Common* TerminalsCOM1–COM41, 4, 10, 13
FUNCTIONNAME
*
NO_/NC_ and COM_ pins are identical and interchangeable. Either may be considered as an input or an output; signals pass equally
well in either direction.
Logic-Control Digital Inputs. Control each switch (see
Truth Tables
), except when
EN is high.
IN1–IN45, 6, 14, 15
MAX4536/MAX4537/MAX4538
__________Applications Information
Power-Supply Considerations
Overview
The MAX4536/MAX4537/MAX4538 construction is typi-
cal of most CMOS analog switches. These devices have
three supply pins: V+, V-, and GND. V+ and V- drive the
internal CMOS switches and set the limits of the analog
voltage on any switch. Reverse ESD-protection diodes
are internally connected between each analog-signal
pin, and both V+ and V-. One of these diodes conducts
if any analog signal exceeds V+ or V-. These reverse-
biased ESD diodes leak during normal operation, form-
ing the only current drawn from V+ or V-.
Virtually all the analog leakage current is through the
ESD diodes. Although the ESD diodes on a given sig-
nal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by
either V+ or V- and the analog signal. This means their
leakages vary as the signal varies. The
difference
in the
two diode leakages from the signal path to the V+ and
V- pins constitutes the analog-signal path leakage cur-
rent. All analog leakage current flows to the supply ter-
minals, not to the other switch terminal. This explains
how both sides of a given switch can show leakage
currents of either the same or opposite polarity.
There is no connection between the analog-signal
paths and GND. The analog-signal paths consist of an
N-channel and P-channel MOSFET with their sources
and drains paralleled and their gates driven out of
phase to V+ and V- by the logic-level translators.
V+ and GND power the internal logic and logic-level
translators and set the input logic thresholds. The
logic-level translators convert the logic levels to
switched V+ and V- signals to drive the analog switch-
es’ gates. This drive signal is the only connection
between the logic supplies and the analog supplies.
V+, and V- have ESD-protection diodes to GND. The
logic-level inputs have ESD protection to V+ and to V-.
Increasing V- has no effect on the logic-level thresh-
olds, but it does increase the drive to the P-channel
switches, reducing their on-resistance. V- also sets the
negative limit of the analog-signal voltage.
The logic-level thresholds are CMOS/TTL-compatible
when V+ is +5V. The threshold increases slightly as V+
is raised. When V+ reaches +12V, the level threshold is
about 3.1V, above the TTL output high-level minimum
of 2.8V, but still compatible with CMOS outputs.
Bipolar Supplies
The MAX4536/MAX4537/MAX4538 operate with bipolar
supplies between ±2.0V and ±6V. The V+ and V- sup-
plies need not be symmetrical, but their sum cannot
exceed the absolute maximum rating of 13.0V. Do not
connect the MAX4536/MAX4537/MAX4538’s V+ to
+3V and then connect the logic-level input pins to
TTL logic-level signals. TTL logic-level outputs in
excess of the absolute maximum ratings can dam-
age the part and/or external circuits.
CAUTION: The absolute maximum V+ to V- differen-
tial voltage is 13.0V. Typical ±6V or +12V supplies
with ±10% tolerances can be as high as 13.2V. This
voltage can damage the MAX4536/MAX4537/MAX4538.
Even ±5% tolerance supplies may have overshoot or
noise spikes that exceed 13.0V.
Single Supplies
The MAX4536/MAX4537/MAX4538 operate from single
supplies between +2.0V and +12V when V- is connect-
ed to GND. All of the bipolar precautions must be
observed.
High-Frequency Performance
In 50systems, signal response is reasonably flat up
to 50MHz (see
Typical Operating Characteristics
).
Above 20MHz, the on-response has several minor
peaks that are highly layout dependent. The problem
with high-frequency operation is not in turning the
switch on, but in turning it off. The off-state switch acts
like a capacitor and passes higher frequencies with
less attenuation. At 10MHz, off-isolation is about -44dB
in 50systems, becoming worse (approximately 20dB
per decade) as frequency increases. Higher circuit
impedances also make off-isolation worse. Adjacent
channel attenuation is about 3dB above that of a bare
IC socket, and is due entirely to capacitive coupling.
Quad, Low-Voltage,
SPST Analog Switches with Enable
8 _______________________________________________________________________________________
MAX4536/MAX4537/MAX4538
Quad, Low-Voltage,
SPST Analog Switches with Enable
_______________________________________________________________________________________ 9
V
GEN
GND
NC or
NO
C
L
V
OUT
V-
V-
V+
V+
V
OUT
IN
OFF
ON
OFF
V
OUT
Q = (V
OUT
)(C
L
)
COM
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
IN
= +3V
R
GEN
IN
MAX4536
MAX4537
MAX4538
Figure 3. Charge Injection
t
r
< 20ns
t
f
< 20ns
50%
0V
LOGIC
INPUT
V-
V-
R
L
300
NO
or NC
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
COM (
R
L
)
R
L
+ R
ON
SWITCH
INPUT
IN, EN
+3V
t
OFF
0V
COM
SWITCH
OUTPUT
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR EN AND SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
C
L
35pF
V+
V+
V
OUT
V
COM
0V
MAX4536
MAX4537
MAX4538
50%
0.9 x V
0UT1
+3V
0V
0V
LOGIC
INPUT
SWITCH
OUTPUT 2
(V
OUT2
)
0V
0.9 x V
OUT2
t
D
t
D
LOGIC
INPUT
V-
V-
R
L2
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
COM2
IN
COM1
V
OUT2
V+
V+
C
L2
V
COM1
= +3V
R
L1
V
OUT1
C
L1
R
L
= 300Ω
C
L
= 35pF
NO1
N02
SWITCH
OUTPUT 1
(V
OUT1
)
MAX4538
V
COM2
= +3V
Figure 1. Switching Time
Figure 2. Break-Before-Make Interval (MAX4538 only)
______________________________________________Test Circuits/Timing Diagrams

MAX4536CEE

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog Switch ICs Quad, Low-Voltage, SPST Analog Switches with Enable
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union