BU17101AKV-ME2

Product structureSilicon monolithic integrated circuit This product is not designed protection against radioactive rays
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TSZ02201-0L2L0HZ00190-1-
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© 2013 ROHM Co., Ltd. All rights reserved.
16.Jan.2013 Rev.001
www.rohm.co.jp
TSZ2211114001
Clockless Link Interface LSI
24bit Clockless Link
Transmitter
BU17101AKV-M
General Description
BU17101AKV-M is a differential serial interface IC that
expect further low power consumption and low EMI by
ROHM's original CDR(Clock Data Recovery) technology.
The BU17101AKV-M transmitter serializes 24-bit
CMOS level signals, and transfers by the differential
lines of 1 pair. There is no return path. Reset line and
link synchronous control line are unnecessary. The
BU17101AKV-M links automatically.
Features
High-speed differential serial interface (Maximum
1.6Gbps)
Embedded clock interface
No lock condition signal and no reset signal between
transmitter and receiver. (Only differential signals)
Low EMI transmission by original DC balance protocol
and scrambling.
Applications
Car navigation display interface
Printer display interface
Key Specifications
I/O voltage range: 2.3 to 3.6 V
3.3V voltage range: 2.3 to 3.6 V
Clock frequency range: 30M to 51M Hz
Transmission data rate: 0.960G to 1.630 Gbps
Effective throughput: 0.720G to 1.224 Gbps
Operating temperature range: -40 to +85
Package W(Typ.) x D(Typ.) x H(Max.)
VQFP48 9.00mm x 9.00mm x 1.63mm
Datasheet
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BU17101AKV-M
TSZ02201-0L2L0HZ00190-1-
2
© 2013 ROHM Co., Ltd. All rights reserved.
16.Jan.2013 Rev.001
www.rohm.co.jp
TSZ2211115001
Block Diagram
Encode
Parallel to Serial
Input Buffer
PLL Timing GenPCLK
PD[23:0]
BU17101AKV-M (Tx)
DFTX+
DFTX-
Operation ControlDFSET[1:0]
PLLBW[1:0]
TESTPT
VDDIO
REG RVDD
GND
Parallel I/O Interface
PD[23:0]
PCLK
ERR
VDD33
TEST[1:0]
POL
Figure 1. Block Diagram
Datasheet
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BU17101AKV-M
TSZ02201-0L2L0HZ00190-1-
2
© 2013 ROHM Co., Ltd. All rights reserved.
16.Jan.2013 Rev.001
www.rohm.co.jp
TSZ2211115001
Typical Application Circuit
PCLK
PD[23:0]
BU17101AKV-M (Tx)
DFTX+
DFTX-
DFRX+(-)
DFRX-(+)
PCLK
PD[23:0]
DFSET1 TEST1
RVDD
POL
TEST0
TESTPT
VDD33
GND
VDDIO
DFSET0
PLLBW0
RVDD
GND
VDDIO
TEST1
POL
TEST0
TESTPT
リセット(Tx)
ストリーム
データ
3.3V
-
+
ストリーム
データ
3.3V
-
+
OE
F_XS
BU17102AKV-M (Rx)
0.1uF
0.1uF
VDD33
0.01uF
0.47uF
0.1uF x 2
1uF
0.01uF
0.47uF
0.1uF x 3
ERR ERR
(47uF)
(47uF)
リセット(Rx)
0.1uF x 20.1uF x 2
0.1uF
0.1uF
PLLBW1
PLLBW1
PLLBW0
Figure 2. Typical Application Circuit
Stream
Data
Stream
Data
Reset(Tx)
Reset(Rx)

BU17101AKV-ME2

Mfr. #:
Manufacturer:
Description:
Interface - Specialized 24bit Clklss Trnsmtr 2.3-3.6V VQFP48
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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