1999 Nov 15 3
Philips Semiconductors Product specification
16-bit buffer/line driver; 3-state
(3.6 V tolerant)
74AVC16244
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; t
r
=t
f
2.0 ns; C
L
=30pF.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
+ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
(C
L
× V
CC
2
× f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
SYMBOL PARAMETER CONDITIONS TYP. UNIT
t
PHL
/t
PLH
propagation delay
nA
n
to nY
n
V
CC
= 1.2 V 2.6 ns
V
CC
= 1.5 V 1.8 ns
V
CC
= 1.8 V 1.7 ns
V
CC
= 2.5 V 1.3 ns
V
CC
= 3.3 V 1.1 ns
C
I
input capacitance 5.0 pF
C
PD
power dissipation
capacitance per buffer
notes 1 and 2
outputs enabled 34 pF
outputs disabled 1 pF
INPUTS OUTPUTS
n
OE nA
n
nY
n
LLL
LHH
HXZ
1999 Nov 15 4
Philips Semiconductors Product specification
16-bit buffer/line driver; 3-state
(3.6 V tolerant)
74AVC16244
ORDERING INFORMATION
PINNING
TYPE NUMBER
PACKAGE
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74AVC16244DGG 40 to +85 °C 48 TSSOP plastic SOT362-1
PIN SYMBOL DESCRIPTION
11
OE output enable input (active LOW)
2, 3, 5 and 6 1Y
0
to 1Y
3
data outputs
4, 10, 15, 21, 28, 34, 39 and 45 GND ground (0 V)
7, 18, 31 and 42 V
CC
positive supply voltage
8, 9, 11 and 12 2Y
0
to 2Y
3
data outputs
13, 14, 16 and 17 3Y
0
to 3Y
3
data outputs
19, 20, 22 and 23 4Y
0
to 4Y
3
data outputs
24 4
OE output enable input (active LOW)
25 3
OE output enable input (active LOW)
26, 27, 29 and 30 4A
3
to 4A
0
data inputs
32, 33, 35 and 36 3A
3
to 3A
0
data inputs
37, 38, 40 and 41 2A
3
to 2A
0
data inputs
43, 44, 46 and 47 1A
3
to 1A
0
data inputs
48 2
OE output enable input (active LOW)
1999 Nov 15 5
Philips Semiconductors Product specification
16-bit buffer/line driver; 3-state
(3.6 V tolerant)
74AVC16244
Fig.3 Pin configuration.
handbook, halfpage
16244
MNA501
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
1Y
0
1Y
1
GND
1Y
2
1Y
3
V
CC
2Y
0
2Y
1
GND
2Y
2
2Y
3
3Y
0
3Y
1
GND
3Y
2
3Y
3
V
CC
4Y
0
4Y
1
GND
4Y
2
4Y
3
4OE
1A
0
1A
1
GND
1A
2
1A
3
V
CC
2A
0
2A
1
GND
2A
2
2A
3
3A
0
3A
1
GND
3A
2
3A
3
V
CC
4A
0
4A
1
GND
4A
2
4A
3
3OE
1OE
2OE
handbook, halfpage
MNA502
nA
3
nA
2
nA
1
nA
0
nY
0
nY
1
nY
2
nY
3
nOE
Fig.4 Logic symbol.
handbook, halfpage
23
MNA503
37
12
11
9
8
6
5
47
46
44
43
41
40
38
2
3
26
22
20
19
17
16
36
35
33
32
30
29
27
13
14
24
4EN
25
3EN
1
1EN
48
2EN
11
31
21
41
Fig.5 IEEE/IEC logic symbol.

74AVC16244DGG,518

Mfr. #:
Manufacturer:
Nexperia
Description:
IC BUF NON-INVERT 3.6V 48TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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