9DBV0431AKILF Datasheet 9DBV0431AKLF, 9DBV0431AKILF, 9DBV0431AKILFT | P10-P12

4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 10 REVISION E 04/28/16

9DBV0431 DATASHEET

General SMBus Serial Interface Information

How to Write

• Controller (host) sends a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through Byte

N+X-1

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

Note: SMBus address is latched on SADR pin.

How to Read

• Controller (host) will send a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) will send a separate start bit

• Controller (host) sends the read address

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N+X-1

• IDT clock sends Byte 0 through Byte X (if X

(H)

was

written to Byte 8)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Write Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

Data Byte Count = X

ACK

Beginning Byte N

X Byte

ACK

Byte N + X - 1

ACK

PstoP bit

Index Block Read Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

RT Repeat starT

Slave Address

RD ReaD

ACK

Data Byte Count=X

ACK

X Byte

Beginning Byte N

ACK

Byte N + X - 1

N Not acknowledge

PstoP bit

REVISION E 04/28/16 11 4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)

9DBV0431 DATASHEET

SMBus Table: Output Enable Register

Byte 0 Name Control Function Type 0 1 Default

Bit 7

Bit 6

DIF OE3 Output Enable RW Low/Low Enabled 1

Bit 5

DIF OE2 Output Enable RW Low/Low Enabled 1

Bit 4

Bit 3

DIF OE1 Output Enable RW Low/Low Enabled 1

Bit 2

Bit 1

DIF OE0 Output Enable RW Low/Low Enabled 1

Bit 0

1. A low on these bits will overide the OE# pin and force the differential output Low/Low

SMBus Table: PLL Operating Mode and Output Amplitude Control Register

Byte 1 Name Control Function Type 0 1 Default

Bit 7

PLLMODERB1 PLL Mode Readback Bit 1

Latch

Bit 6

PLLMODERB0 PLL Mode Readback Bit 0

Latch

Bit 5

PLLMODE_SWCNTRL Enable SW control of PLL Mode RW

Values in B1[7:6]

set PLL Mode

Values in B1[4:3]

set PLL Mode

Bit 4

PLLMODE1 PLL Mode Control Bit 1

Bit 3

PLLMODE0 PLL Mode Control Bit 0

Bit 2

Bit 1

AMPLITUDE 1 RW 00 = 0.6V 01 = 0.7V 1

Bit 0

AMPLITUDE 0 RW 10= 0.8V 11 = 0.9V 0

1. B1[5] must be set to a 1 for these bits to have any effect on the part.

SMBus Table: DIF Slew Rate Control Register

Byte 2 Name Control Function Type 0 1 Default

Bit 7

Bit 6

SLEWRATESEL DIF3 Slew Rate Selection RW 2 V/ns 3 V/ns 1

Bit 5

SLEWRATESEL DIF2 Slew Rate Selection RW 2 V/ns 3 V/ns 1

Bit 4

Bit 3

SLEWRATESEL DIF1 Slew Rate Selection RW 2 V/ns 3 V/ns 1

Bit 2

Bit 1

SLEWRATESEL DIF0 Slew Rate Selection RW 2 V/ns 3 V/ns 1

Bit 0

SMBus Table: Frequency Select Control Register

Byte 3 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

FREQ_SEL_EN

Enable SW selection of

frequency

SW frequency

change disabled

SW frequency

change enabled

Bit 4

FSEL1 Freq. Select Bit 1

Bit 3

FSEL0 Freq. Select Bit 0

Bit 2

Bit 1

Bit 0

SLEWRATESEL FB Adjust Slew Rate of FB RW 2 V/ns 3 V/ns 1

1. B3[5] must be set to a 1 for these bits to have any effect on the part.

Byte 4 is Reserved and reads back 'hFF

See PLL Operating Mode Table

Reserved

See PLL Operating Mode Table

Reserved

See Frequency Select Table

Controls Output Amplitude

Reserved

4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 12 REVISION E 04/28/16

9DBV0431 DATASHEET

SMBus Table: Revision and Vendor ID Register

Byte 5 Name Control Function Type 0 1 Default

Bit 7

RID3

Bit 6

RID2

Bit 5

RID1

Bit 4

RID0

Bit 3

VID3

Bit 2

VID2

Bit 1

VID1

Bit 0

VID0

SMBus Table: Device Type/Device ID

Byte 6 Name Control Function Type 0 1 Default

Bit 7

Device Type1

Bit 6

Device Type0

Bit 5

Device ID5

Bit 4

Device ID4

Bit 3

Device ID3

Bit 2

Device ID2

Bit 1

Device ID1

Bit 0

Device ID0

SMBus Table: Byte Count Register

Byte 7 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

BC4 RW 0

Bit 3

BC3 RW 1

Bit 2

BC2 RW 0

Bit 1

BC1 RW 0

Bit 0

BC0 RW 0

000100 binary or 04 hex

00 = FGV, 01 = DBV,

10 = DMV, 11= Reserved

Byte Count Programming

A rev = 0000Revision ID

0001 = IDT

Device Type

Writing to this register will configure how

many bytes will be read back, default is

= 8 bytes.

Reserved

VENDOR ID

Device ID

Reserved

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

9DBV0431AKILF

Mfr. #:

Buy 9DBV0431AKILF

Manufacturer:

IDT

Description:

Clock Buffer 4 O/P 1.8V PCIE BUFFER

Lifecycle:

New from this manufacturer.

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9DBV0431AKILF

9DBV0431AKILF

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