LTC4364-1/LTC4364-2
16
436412f
Then:
P
2
t =I
LOAD
2
1
3
t
r
b a
( )
3
b
+
1
2
τ 2a
2
In
b
a
+ 3a
2
+ b
2
4ab
Typically V
REG
≈ V
IN
and τ >> t
r
simplifying the above to:
P
2
t =
1
2
I
LOAD
2
V
PK
V
REG
( )
2
τ
For the transient conditions of V
PK
= 80V, V
IN
= 12V, V
REG
= 16V, t
r
= 10μs and τ = 1ms, and a load current of 3A,
P
2
t is 18.4W
2
s—easily handled by a MOSFET in a D-pak
package. The P
2
t of other transient waveshapes is evalu-
ated by integrating the square of MOSFET power versus
time. LTSpice™ can be used to simulate timer behavior
for more complex transients and cases where overvoltage
and overcurrent faults coexist.
Short-Circuit Stress
SOA stress of M1 must also be calculated for output short-
circuit conditions. Short-circuit P
2
t is given by:
P
2
t = V
IN
V
SNS
R
SNS
2
t
OC
where V
SNS
is the overcurrent fault threshold and t
OC
is
the overcurrent timer interval.
For V
IN
= 15V, OUT = 0V, V
SNS
= 25mV, R
SNS
= 12mΩ
and C
TMR
= 100nF, P
2
t is 2.2W
2
s—less than the transient
SOA calculated in the previous example. Nevertheless,
to account for circuit tolerances this figure should be
doubled to 4.4W
2
s.
Limiting Inrush Current and HGATE Pin Compensation
The LTC4364 limits the inrush current to any load capaci-
tance by controlling the HGATE pin voltage slew rate. An
external capacitor, C
HG
, can be connected from HGATE
to ground to slow down the inrush current further at the
expense of slower turn-off time. The gate capacitor is set at:
C
HG
=
I
HGATE(UP)
I
INRUSH
C
L
where I
HGATE(UP)
is the HGATE pin pull-up current, I
INRUSH
is the desired inrush current, C
L
is total load capacitance
at the output. In typical applications, a C
HG
of 6.8nF is
recommended for loop compensation during overvoltage
and overcurrent events. With input voltage steps faster
than 5V/μs, a larger gate capacitor helps prevent self
enhancement of the N-channel MOSFET.
The added gate capacitor slows down the turn-off time
during fault conditions and allows higher peak currents to
build up during an output short event. If this is a concern,
an extra resistor, R6, in series with C
HG
can restore the
turn-off time. A diode, D5, should be placed across R6
with the cathode connected to C
HG
as shown in Figure 1.
In a fast transient input step, D5 provides a bypass path to
C
HG
for the benefit of holding HGATE low and preventing
self enhancement.
Shutdown
The LTC4364 can be shut down to a low current mode
by pulling SHDN below 0.5V. The quiescent V
CC
current
drops to 10μA for both the LTC4364-1 and the LTC4364-2.
The SHDN pin can be pulled up to 100V or below GND by
up to 40V without damage. Leaving the pin open allows
an internal current source to pull it up to about 4V and
turn the part on. The leakage current at the pin should be
limited to no more than 1μA if no pull-up device is used
to help turn it on.
Supply Transient Protection
The LTC4364 is tested to operate to 80V and guaranteed
to be safe from damage between 100V and −40V. Voltage
transients above 100V or below −40V may cause permanent
damage. During a short-circuit condition, the large change
in current flowing through power supply traces coupled
with parasitic inductances from associated wiring can
cause destructive voltage transients in both positive and
negative directions at the V
CC
, SOURCE, and OUT pins. To
reduce the voltage transients, minimize the power trace
parasitic inductance by using short, wide traces. A small
RC filter (R4 and C1 in Figure 1) at the V
CC
pin filters high
voltage spikes of short pulse width.
APPLICATIONS INFORMATION
LTC4364-1/LTC4364-2
17
436412f
Another way to limit supply transients above 100V at the
V
CC
pin is to use a Zener diode and a resistor, D1 and R4,
as shown in Figure 1. D1 clamps voltage spikes at the V
CC
pin while R4 limits the current through D1 to a safe level
during the surge. In the negative direction, D1 along with
R4 clamps the V
CC
pin near GND. The inclusion of R4 in
series with the V
CC
pin increases the minimum required
supply voltage due to the extra voltage drop across the
resistor, which is determined by the supply current of the
LTC4364 and the leakage current of D1. 2.2k adds about
1V to the minimum operating voltage.
For sustained, elevated suppy voltages, the power dissipa-
tion of R4 becomes unacceptable. This can be resolved
by using an external NPN transistor (Q1 in Figure 7) as
a buffer. To protect Q1 against supply reversal, block the
collector of Q1 with a series diode or tie it to the cathode
of D3 and D4 in Figure 1.
Transient suppressor D3 in Figure 1 clamps the input
voltage to 200V for voltage transients higher than 200V,
to prevent breakdown of M1. It also blocks forward con-
duction in D4. D4 limits the SOURCE pin voltage to 24V
below GND when the input goes negative. C
OUT
helps
absorb the inductive energy at the output upon a sudden
input short, protecting the OUT and SENSE pins.
Output Port Protection
In applications where the output is on a connector, as
shown in Figure 14, if the output is plugged into a supply
that is higher than the input, the ideal diode MOSFET, M2,
turns off to open the backfeeding path. In the case where
the output port is plugged into a supply that is below GND,
the SOURCE pin is pulled below GND through the body
diode of M2. The LTC4364 responds to this condition by
shorting the HGATE pin to the SOURCE pin, turning M1
off and shutting down the current path from V
IN
to V
OUT
.
Design Example
As a design example, consider an application with the
following specifications: V
IN
= 8V to 14V DC with a peak
transient of 200V and decay time constant τ of 1ms, V
OUT
≤ 27V, minimum current limit I
LIM(MIN)
at 4A, low-battery
detection at 6V, input overvoltage level at 60V, and 1ms
of overvoltage early warning (Figure 1).
Selection of CMZ5945B for D1 will limit the voltage at
the V
CC
pin to less than 71V during the 200V surge. The
minimum required voltage at the V
CC
pin is 4V when V
IN
is
at 6V; the maximum supply current for LTC4364 is 750μA.
The maximum value for R4 to ensure proper operation is:
R4 =
6V 4V
0.75mA
= 2.7k
Select 2.2k for R4 to accommodate all conditions.
With the minimum Zener voltage at 64V, the peak current
through R4 into D1 is then calculated as:
I
D1(PK)
=
200V 64V
2.2k
= 62mA
which can be handled by the CMZ5945B with a peak power
rating of 200W at 10/1000μs.
With a bypass capacitance of 0.1μF (C1), along with R4
of 2.2k, high voltage transients up to 250V with a pulse
width less than 20μs are filtered out at the V
CC
pin.
Next, calculate the resistive divider value to limit V
OUT
to
27V during an overvoltage event:
V
REG
=
1.25V R7+ R8
( )
R8
= 27V
APPLICATIONS INFORMATION
V
CC
LTC4364
GND
436412 F07
C1
100nF
Q1
PZTA42
V
IN
200V
D1
CMZ5945B
68V
R4
22k
1/4W
Figure 7. Buffering V
CC
to Extend Input Supply Range
Output Bypassing
The OUT and SENSE pins can withstand up to 100V above
and 20V below GND. In all applications the output must
be bypassed with at least 22μF low ESR electrolytic (C
OUT
in Figure 1) to stabilize the voltage and current limiting
loops, and to minimize capacitive feedthrough of input
transients. Total ceramic bypassing of up to one-tenth
the total electrolytic capacitance is permissible without
compromising performance.
LTC4364-1/LTC4364-2
18
436412f
Choosing 250μA for the resistive divider:
R8 =
1.25V
250µA
= 5k
Select 4.99k for R8.
R7 =
27V 1.25V
( )
R8
1.25V
= 102.8k
The closest standard value for R7 is 102k.
Now, calculate the sense resistor, R
SNS
, value:
R
SNS
=
V
SNS(MIN)
I
LIM
=
45mV
4A
= 11m
Choose 10mΩ for R
SNS
.
C
TMR
is then chosen for 1ms of early warning time:
C
TMR
=
1ms 5µA
100mV
= 50nF
The closest standard value for C
TMR
is 47nF.
Finally, calculate R1, R2 and R3 for 6V low battery detec-
tion and 60V input overvoltage level:
6V
R1+R2+R3
=
1.25V
R2+ R3
60V
R1+R2+R3
=
1.25V
R3
Simplify the equations and choose 10k for R3 to get:
R2=
60V
6V
1
R3 = 9 R3= 90k
R1=
6V
1.25V
1
R2+R3
( )
= 3.8 R1+R2
( )
= 380k
Select 90.9kΩ for R2 and 383kΩ for R1.
The pass device, M1, should be chosen to withstand an
output short condition with V
CC
= 14V. In the case of a
severe output short where V
OUT
= 0V, I
TMR(UP)
= 55μA and
the total overcurrent fault time is:
t
OC
=
C
TMR
V
TMR(G)
I
TRM(UP)
=
47nF 1.35V
55µA
= 1.15ms
The maximum power dissipation in M1 is:
P =
V
DS(M1)
V
SNS(MAX)
R
SNS
=
14V 32mV
10m
= 45W
The corresponding P
2
t is 2.3W
2
s.
During an output overload or soft short, the voltage at the
OUT pin could stay at 2V or higher. The total overcurrent
fault time when V
OUT
= 2V is:
t
OC
=
47nF 1.35V
49µA
= 1.3ms
The maximum power dissipation in M1 is:
P =
14V 2V
( )
55mV
10m
= 66W
The corresponding P
2
t is 5.7W
2
s. Both of the above condi-
tions are well within the safe operating area of FDB33N25.
To select the pass device, M2, first calculate R
DS(ON)
to
achieve the desired forward drop V
FW
at maximum load
current (5.5A). If V
FW
= 0.25V:
R
DS(ON)
V
FW
I
LOAD(MAX)
=
0.25V
5.5A
= 45.5m
The FDB3682 offers a maximum R
DS(ON)
of 36mΩ at
V
GS
= 10V so is a good fit. Its minimum BV
DSS
of 100V
is also sufficient to handle V
OUT
transients up to 100V
during an input short-circuit event.
Layout Considerations
To achieve accurate current sensing, use Kelvin connections
to the current sense resistor, R
SNS
. Limit the resistance
from the SOURCE pin to the sources of the MOSFETs to
below 10Ω. The minimum trace width for 1oz copper foil
is 0.02" per amp to ensure the trace stays at a reason-
able temperature. Note that 1oz copper exhibits a sheet
resistance of about 530μΩ/square. Small resistances can
cause large errors in high current applications. Noise im-
munity will be improved significantly by locating resistive
dividers close to the pins with short V
CC
and GND traces.
APPLICATIONS INFORMATION

DC2027A-B

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Management IC Development Tools LTC4364DE-2 Demoboard: 12V Surge Stopper
Lifecycle:
New from this manufacturer.
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