© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 0
1
Publication Order Number:
NB7L585R/D
NB7L585R
2.5V/3.3V, 7GHz/10Gbps
Differential 2:1 Mux Input to
1:6 RSECL Clock/Data
Fanout Buffer / Translator
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L585R is a differential 1:6 RSECL Clock/Data distribution
chip featuring a 2:1 Clock/Data input multiplexer with an input select
pin. The INx/INx
inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels.
The NB7L585R produces six identical output copies of Clock or
Data operating up to 7 GHz or 10 Gb/s, respectively. As such,
NB7L585R is ideal for SONET, GigE, Fiber Channel, Backplane and
other Clock/Data distribution applications.
The NB7L585R is powered with either 2.5 V or 3.3 V supply and is
offered in a low profile 5mm x 5mm 32−pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7L585R is a member of the GigaComm™ family of high
performance clock products.
Features
• Maximum Input Data Rate > 10 Gb/s Typical
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 7 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
• Low Skew 1:6 RSECL Outputs, 20 ps max
• 2:1 Multi−Level Mux Inputs
• 160 ps Typical Propagation Delay
• 40 ps Typical Rise and Fall Times
• Differential RSECL Outputs, 400 mV peak−to−peak, typical
• Operating Range: V
CC
= 2.375 V to 3.6 V with GND = 0 V
• Internal 50 W Input Termination Resistors
• VREFAC Reference Output
• QFN−32 Package, 5mm x 5mm
• −40ºC to +85ºC Ambient Operating Temperature
• These Devices are Pb−Free and are RoHS Compliant
QFN32
MN SUFFIX
CASE 488AM
See detailed ordering and shipping information on page 8 of
this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
http://onsemi.com
32
1
NB7L
585R
AWLYYWWG
G
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
50 W
50 W
IN1
VT1
IN1
50 W
50 W
IN0
VT0
IN0
Figure 1. Simplified Block Diagram
0
1
VREFAC1
VREFAC0
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
V
CC
GND
+
SEL
