IDT
TM
/ICS
TM
Frequency Gearing Clock for
CPU, PCIe Gen1, Gen2, & FBD 1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
22
INDEX
AREA
12
N
D
E1
E
a
SEATING
PLANE
A1
A
A2
e
-C-
b
c
L
aaa C
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
α
8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
56 13.90 14.10 .547 .555
10-0039
N
D mm. D (inch)
Reference Doc.: JEDEC Publication 95, M O-153
0.50 BASIC 0.020 BASIC
SEE VARIATIONS SEE VARIATIONS
SEE VARIATIONS SEE VARIATIONS
8.10 BASIC 0.319 BASIC
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
Ordering Information
Part / Order Number Shipping/Packaging Package Temperature
9FG1201HGLF Tubes 56-pin TSSOP 0 to +70°C
9FG1201HGLFT Tape and Reel 56-pin TSSOP 0 to +70°C
9FG1201HFLF Tubes 56-pin SSOP 0 to +70°C
9FG1201HFLFT Tape and Reel 56-pin SSOP 0 to +70°C
"LF" denotes Pb free packaging, RoHS compliant
"H" denotes revision designator (will not correlate with datasheet revision)
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
23
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
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Printed in USA
TM
Revision History
Rev. Issue Date Description Page #
A 10/22/2007 Release to Final. -
B 1/29/2008
Updated Key Specifications:
Changed units for DIF output-to-output skew to "ps".
1
C 2/12/2008
Changed Cin value from 6 pf to 5 pf.
14
D 9/24/2008 Added 1:1 VCO Programming Table 6
E 1/21/2009 Updated Skew and Phase Jitter tables. 17,18
F 9/23/2009 Updated Ordering Information table 22

9FG1201HGLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 12 Output PCIe Gearng Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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