MPC962308D-1H Datasheet MPC962308D-1, MPC962308DT-1H, MPC962308D-1H | P4-P6

MPC962308

TIMING SOLUTIONS 4 MOTOROLA

Table 5. Operating Conditions for MPC962308-X Industrial Temperature Devices

Parameter Description Min Max Unit

V

DD

Supply Voltage 3.0 3.6 V

T

A

Operating Temperature (Ambient Temperature) –40 85 °C

C

L

Load Capacitance, below 100 MHz 30 pF

Load Capacitance, from 100 MHz to 133 MHz 15 pF

C

IN

Input Capacitance

1

1. Applies to both REF clock and FBK.

7pF

Table 6. Electrical Characteristics for MPC962308-X Industrial Temperature Devices

1

1. All parameters are specified with loaded outputs.

Parameter Description Test Conditions Min Max Unit

V

IL

Input LOW Voltage 0.8 V

V

IH

Input HIGH Voltage 2.0 V

I

IL

Input LOW Current V

IN

= 0V 50.0 µA

I

IH

Input HIGH Current V

IN

= V

DD

100.0 µA

V

OL

Output LOW Voltage

2

2. Parameter is guaranteed by design and characterization. Not 100% tested in production.

I

OL

= 8 mA (-1, -2, -3, -4)

I

OL

= 12 mA (-1H, -5H)

0.4 V

V

OH

Output HIGH Voltage

2

I

OH

= -8 mA (-1, -2, -3, -4)

I

OH

= -12 mA (-1H, -5H)

2.4 V

I

DD

(PD mode) Power Down Supply Current REF = 0 MHz 25.0 µA

I

DD

Supply Current Unloaded outputs, 100 MHz,

Select inputs at V

DD

or GND

45.0 mA

70(-1H, -5H) mA

Unloaded outputs, 66-MHz REF

(-1, -2, -3, -4)

35.0 mA

Unloaded outputs, 35-MHz REF

(-1, -2, -3, -4)

20.0 mA

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MPC962308

MOTOROLA 5 TIMING SOLUTIONS

Table 7. Switching Characteristics for MPC962308-X Industrial Temperature Devices

1

1. All parameters are specified with loaded outputs.

Parameter Name Test Conditions Min Typ Max Unit

t

1

Output Frequency 30-pF load, All devices 10 100 MHz

t

1

Output Frequency

2

2. Parameter is guaranteed by design and characterization. Not 100% tested in production.

20-pF load, -1H, -5H devices 10 133.3 MHz

t

1

Output Frequency

2

15-pF load, -1, -2, -3, -4 devices 10 133.3 MHz

Duty Cycle

2

= t

2

÷ t

1

(-1, -2, -3, -4, -1H, -5H)

Measured at 1.4 V, FOUT =66.66 MHz

30-pF load

40.0 60.0 %

Duty Cycle

2

= t

2

÷ t

1

(-1, -2, -3, -4, -1H, -5H)

Measured at 1.4 V, FOUT <50.0 MHz

15-pF load

45.0 55.0 %

t

3

Rise Time

2

(-1, -2, -3, -4)

Measured between 0.8 V and 2.0 V,

30-pF load

2.50 ns

Rise Time

2

(-1, -2, -3, -4)

Measured between 0.8 V and 2.0 V,

15-pF load

1.50 ns

Rise Time

2

(-1H, -5H)

Measured between 0.8 V and 2.0 V,

30-pF load

1.50 ns

t

4

Fall Time

2

(-1, -2, -3, -4)

Measured between 0.8 V and 2.0 V,

30-pF load

2.50 ns

Fall Time

2

(-1, -2, -3, -4)

Measured between 0.8 V and 2.0 V,

15-pF load

1.50 ns

Fall Time

2

(-1H, -5H)

Measured between 0.8 V and 2.0 V,

30-pF load

1.25 ns

Output-to-Output Skew on

same Bank (-1, -2, -3, -4)

2

All outputs equally loaded

200 ps

t

5

Output-to-Output Skew

(-1H, -5H)

All outputs equally loaded 200 ps

Output Bank A to Output

Bank B Skew (-1, -4, -5H)

All outputs equally loaded 200 ps

Output Bank A to Output

Bank B Skew (-2, -3)

All outputs equally loaded 400 ps

t

6

Delay, REF Rising Edge to

FBK Rising Edge

2

Measured at V

DD

/2 0 ±250 ps

t

7

Device-to-Device Skew

2

Measured at V

DD

/2 on the FBK pins of devices 0 700 ps

t

8

Output Slew Rate

2

Measured between 0.8 V and 2.0 V on -1H,

-5H device using Test Circuit # 2

1 V/ns

t

J

Cycle-to-Cycle Jitter

(-1, -1H, -4, -5H)

2

Measured at 66.67 MHz, loaded outputs,

15-pF load

200 ps

Measured at 66.67 MHz, loaded outputs,

30-pF load

200 ps

Measured at 133.3 MHz, loaded outputs,

15 pF load

100 ps

t

J

Cycle-to-Cycle Jitter

(-2, -3)

2

Measured at 66.67 MHz, loaded outputs

30-pF load

400 ps

Measured at 66.67 MHz, loaded outputs

15-pF load

400 ps

t

LOCK

PLL Lock Time

2

Stable power supply, valid clocks presented

on REF and FBK pins

1.0 ms

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MPC962308

TIMING SOLUTIONS 6 MOTOROLA

APPLICATIONS INFORMATION

Figure 1. Output-to-Output Skew t

SK(O)

Figure 2. Static Phase Offset Test Reference

Figure 3. Output Duty Cycle (DC)

V

CC

V

CC

÷ 2

GND

V

CC

V

CC

÷ 2

GND

t

6

CCLK

FB_IN

The pin-to-pin skew is defined as the worst case difference in propagation

delay between any similar delay path within a single device

V

CC

1.4 V

GND

V

CC

1.4 V

GND

t

5

The time from the PLL controlled edge to the non-controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

V

CC

1.4 V

GND

t

2

t

1

DC = t

2

/t

1

x 100%

Figure 5. Cycle-to-Cycle Jitter

t

4

t

3

V

CC

= 3.3 V

2.0

0.8

Figure 6. Output Transition Time Test Reference

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs

t

N

t

J

= |t

N

–t

N+1

|

t

N+1

Figure 4. Device-to-Device Skew

V

CC

V

CC

÷ 2

GND

V

CC

V

CC

÷ 2

GND

t

7

DEVICE 1

DEVICE 2

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MPC962308D-1H

MPC962308D-1H

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