XC95288 In-System Programmable CPLD
DS069 (v4.3) April 3, 2006 www.xilinx.com 5
Product Specification
R
Internal Timing Parameters
Symbol Parameter
XC95288-15 XC95288-20
UnitsMin Max Min Max
Buffer Delays
T
IN
Input buffer delay - 4.5 - 6.5 ns
T
GCK
GCK buffer delay - 3.0 - 3.0 ns
T
GSR
GSR buffer delay - 7.5 - 9.5 ns
T
GTS
GTS buffer delay - 11.0 - 16.0 ns
T
OUT
Output buffer delay - 4.5 - 6.5 ns
T
EN
Output buffer enable/disable delay - 0 - 0 ns
Product Term Control Delays
T
PTCK
Product term clock delay - 2.5 - 2.5 ns
T
PTSR
Product term set/reset delay - 3.0 - 3.0 ns
T
PTTS
Product term 3-state delay - 5.0 - 5.0 ns
Internal Register and Combinatorial Delays
T
PDI
Combinatorial logic propagation delay - 3.0 - 4.0 ns
T
SUI
Register setup time 3.5 - 3.5 - ns
T
HI
Register hold time 4.5 - 6.5 - ns
T
COI
Register clock to output valid time - 0.5 - 0.5 ns
T
AOI
Register async. S/R to output delay - 8.0 - 8.0 ns
T
RAI
Register async. S/R recover before clock 10.0 - 10.0 - ns
T
LOGI
Internal logic delay - 3.0 - 3.0 ns
T
LOGILP
Internal low power logic delay - 11.5 - 11.5 ns
Feedback Delays
T
F
FastCONNECT feedback delay - 11.0 - 13.0 ns
T
LF
Function block local feedback delay - 3.5 - 5.0 ns
Time Adders
T
PTA
(1)
Incremental product term allocator delay - 1.0 - 1.5 ns
T
SLEW
Slew-rate limited delay - 5.0 - 5.5 ns
Notes:
1. T
PTA
is multiplied by the span of the function as defined in the XC9500 family data sheet.
