CPC7695ZBTR Datasheet CPC7695BC, CPC7695ZCTR, CPC7695BCTR | P16-P18

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2. Functional Description

2.1 Introduction

The CPC7695 has the following states:

• Talk. Loop break switches SW1 and SW2 closed, all

other switches open.

• Ringing. Ringing switches SW3 and SW4 closed, all

other switches open.

• TESTout. Testout switches SW5 and SW6 closed,

all other switches open.

• Ringing generator test. SW7 and SW8 closed, all

other switches open.

• TESTin. Testin switches SW9 and SW10 closed, all

other switches open.

• Simultaneous TESTin and TESTout. SW9, SW10,

SW5, and SW6 closed, all other switches open.

• Simultaneous TESTout and Ringing generator

test. SW5, SW6, SW7, and SW8 closed, all other

switches open (only on the xC and xD versions).

• All-Off. All switches open.

See “Truth Tables” on page 15 for more information.

The CPC7695 offers break-before-make and

make-before-break switching from the Ringing state to

theTalk state with simple TTL level logic input control.

Solid-state switch construction means no impulse

noise is generated when switching during ringing

cadence or ring trip, eliminating the need for external

zero-cross switching circuitry. State-control is via TTL

logic-level input so no additional driver circuitry is

required. The linear line break switches SW1 and

SW2 have exceptionally low R

and excellent

matching characteristics. The ringing switch, SW4,

has a minimum open contact breakdown voltage of

465V at +25°C, sufficiently high with proper protection

to prevent breakdown in the presence of a transient

fault condition (i.e., prevent passing the transient on to

the ringing generator).

Integrated into the CPC7695 is an over-voltage

clamping circuit, active current limiting, and a thermal

shutdown mechanism to provide protection to the

SLIC during a fault condition. Positive and negative

lightning surge currents are reduced by the current

limiting circuitry and hazardous potentials are diverted

away from the SLIC via the protection diode bridge or

the optional integrated protection SCR. Power-cross

potentials are also reduced by the current limiting and

thermal shutdown circuits.

To protect the CPC7695 from an overvoltage fault

condition, the use of a secondary protector is required.

The secondary protector must limit the voltage seen at

the T

LINE

and R

LINE

terminals to a level below the

maximum breakdown voltage of the switches. To

minimize the stress on the solid-state contacts, use of

a foldback or crowbar type secondary protector is

highly recommended. With proper selection of the

secondary protector, a line card using the CPC7695

will meet all relevant ITU, LSSGR, TIA/EIA and IEC

protection requirements.

The CPC7695 operates from a single +5V supply only.

This gives the device extremely low idle and active

power consumption with virtually any range of battery

voltage. The battery voltage used by the CPC7695

has a two fold function. For protection purposes it is

used as a fault condition current source by the internal

integrated protection circuitry. Secondly, it is used as a

reference so that in the event of battery voltage loss,

the CPC7695 will enter the All-Off state.

2.2 Start-up

The CPC7695 uses smart logic to monitor the V

supply. Any time V

is below an internally set

threshold, the smart logic places the control logic into

the All-Off state. An internal pullup on the LATCH pin

locks the CPC7695 in the All-Off state following

start-up until the LATCH pin is pulled down to a logic

low. Prior to the assertion of a logic low at the LATCH

pin, the switch control inputs must be properly

conditioned.

2.3 Data Latch

The CPC7695 has an integrated transparent data

latch. Operation of the latch enable is controlled by

TTL logic input levels at the LATCH pin. Data input to

the latch are via the input pins, while the output of the

data latch are internal nodes used for state control.

When the LATCH enable control pin is at logic 0 the

data latch is transparent and the input data control

signals flow directly through the latch to the state

control circuitry. A change in input will be reflected by a

change in switch state. Whenever the LATCH enable

control pin is at logic 1, the latch is active and data is

locked. Subsequent input changes will not result in a

change to the control logic or affect the existing switch

state.

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Switches will remain in the state they were in when the

LATCH pin changes from logic 0 to logic 1 and will not

respond to changes in input as long as the latch is at

logic 1. However, neither the T

input nor the T

output control functions are affected by the latch

function. Internal thermal shutdown control and

external “All-Off” control via T

is not affected by the

state of the LATCH enable input.

2.4 T

Pin Description

The T

pin is a bidirectional I/O structure with an

internal pull up sourced from V

. As an output, this

pin indicates the status of the thermal shutdown

circuitry. Typically, during normal operation, this pin will

be pulled up to V

but under fault conditions that

create excess thermal loading the CPC7695 will enter

thermal shutdown and a logic low will be output.

As an input, the T

pin can be utilized to place the

CPC7695 into the “All-Off” state by simply pulling the

input low via an open-collector type buffer. Using a

standard output having an active logic high drive

capability will need to sink the T

pull-up current to

attain a logic low resulting in unnecessary power

consumption.

Use of a standard output buffer with an active high

drive capability, or tying T

to V

, will not disable the

thermal shutdown mechanism. The ability to enter

thermal shutdown during a fault condition is

independent of the connection at the T

input.

The CPC7695’s internal pull up has a nominal value of

16A.

2.5 Under Voltage Switch Lock Out Circuitry

2.5.1 Overview

Smart logic in the CPC7695 now provides for switch

state control during both power-up and power-loss

transitions. An internal detector is used to evaluate the

supply to determine when to de-assert the under

voltage switch lock out circuitry with a rising V

and

when to assert the under voltage switch lock out

circuitry with a falling V

. Any time unsatisfactory low

conditions exist, the lock out circuit overrides user

switch control by blocking the information at the

external input pins and conditioning internal switch

commands to the All-Off state. Upon restoration of

, the switches will remain in the All-Off state until

the LATCH input is pulled low.

The rising V

switch lock-out release threshold is

internally set to ensure all internal logic is properly

biased and functional before accepting external switch

commands at the inputs to control the switch states.

For a falling V

event, the lock-out threshold is set to

assure proper logic and switch behavior up to the

moment the switches are forced off and external

inputs are suppressed.

To facilitate hot plug insertion and system power-up

state control, the LATCH pin has an integrated weak

pull up resistor to the V

power rail that will hold a

non-driven LATCH pin at a logic high state. This

enables board designers to use the CPC7695 with

FPGAs and other devices that provide high

impedance outputs during power-up and logic

configuration. The weak pull up allows a fan out of up

to 32 when the system’s LATCH control driver has a

logic low minimum sink capability of 4mA.

2.5.2 Hot-Plug and Power-Up Design Considerations

There are six possible start up scenarios that can

occur during power-up. They are:

1. All inputs defined at power-up & LATCH = 0

2. All inputs defined at power-up & LATCH = 1

3. All inputs defined at power-up & LATCH = Z

4. All inputs not defined at power-up & LATCH = 0

5. All inputs not defined at power-up & LATCH = 1

6. All inputs not defined at power-up & LATCH = Z

Under all of the start up situations listed above the

CPC7695 will hold all of it’s switches in the All-Off

state during power-up. When V

requirements have

been satisfied the LCAS will complete it’s start up

procedure in one of three conditions.

For start up scenario 1, the CPC7695 will transition

from the All-Off state to the state defined by the inputs

when V

is valid.

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For start up scenarios 2, 3, 5, and 6 the CPC7695 will

power up in the All-Off state and remain there until the

LATCH pin is pulled low. This allows for an indefinite

All-Off state for boards inserted into a powered system

but are not configured for service or boards that need

to wait for other devices to be configured first.

Start up scenario 4 will start up with all switches in the

All-Off state but upon the acceptance of a valid V

the LCAS will revert to any one of the legitimate states

listed in the truth tables and there after may randomly

change states based on input pin leakage currents

and loading. Because the LCAS state after power-up

can not be predicted with this start up condition it

should never be utilized.

On designs that do not wish to individually control the

LATCH pins of multi-port cards it is possible to bus

many (or all) of the LATCH pins together to create a

single board level input enable control.

2.6 V

BAT

2.6.1 Protection

2.6.2 Battery Voltage Monitor

The CPC7695 also uses the V

BAT

pin to monitor

battery voltage. If the system battery voltage is lost,

the CPC7695 immediately enters the All-Off state. It

remains in this state until the system battery voltage is

restored. The device also enters the All-Off state if the

battery voltage rises more positive than about –10V

and remains in the All-Off state until the battery

voltage drops below –15 V. This battery monitor

feature draws a small current from the battery (less

than 1 A typical) and will add slightly to the device’s

overall power dissipation.

This monitor function performs properly if the

CPC7695 and SLIC share a common battery supply

origin. Otherwise, if battery is lost to the CPC7695 but

not to the SLIC, the V

BAT

pin will be internally biased

by the potential applied to the T

BAT

or R

BAT

pins via

the internal protection circuitry’s SCR trigger current

path.

2.7 Ringing To Talk State Switch Timing

The CPC7695 provides, when switching from the

Ringing state to theTalk state, the ability to control the

release timing of the ringing switches SW3 and SW4

relative to the state of the break switches SW1 and

SW2 using simple TTL logic-level inputs. The two

available techniques are referred to as

make-before-break and break-before-make operation.

When the switch contacts of SW1 and SW2 are closed

(made) before the ringing switch contacts of SW3 and

SW4 are opened (broken), this is referred to as

make-before-break operation. Break-before-make

operation occurs when the ringing contacts of SW3

and SW4 are opened (broken) before the switch

contacts of SW1 and SW2 are closed (made). With

the CPC7695, make-before-break and

break-before-make operations can easily be

accomplished by applying the proper sequence of

logic-level inputs to the device.

The logic sequences for either mode of operation are

given in “Operation Logic Table (Ringing to Talk Transition):

Make-Before-Break” on page 19, “Operation Logic Table

(Ringing to Talk Transition): Break-Before-Make” on page 19

and “Alternate Operation Logic Table (Ringing to Talk

Transition): Break-Before-Make” on page 20. Logic states

and explanations are shown in “Truth Tables” on

page 15.

2.7.1 Make-Before-Break Operation

To use make-before-break operation, change the logic

inputs from the Ringing state directly to theTalk state.

Application of theTalk state opens the ringing return

switch, SW3, as the break switches SW1 and SW2

close. The ringing switch, SW4, remains closed until

the next zero-crossing of the ringing current. While in

the make-before-break state, ringing potentials in

excess of the CPC7695 internal protection circuitry

thresholds will be diverted away from the SLIC.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

CPC7695ZBTR

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Switch ICs - Various LCAS w/ NO SCR 20-Pin SOIC

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