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NCP5212AGEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
NCP5212A, NCP5212T
http://onsemi.com
4
VOUT1
GND1
VIN
EN=VEN_Master
16
9
1
2
3
4
5
12
10
11
876
15 14 13
VIN
VCC
SYN
FB
CS−/Vo
CS+
PGND
DL/TRESET
VCCP
BST
DH
SWN
PGOOD
AGND
COMP
IDRP/OCP
NCP5212A/
EN
5V
VOUT2
GND2
PGOOD2
16
9
1
2
3
4
5
12
10
11
876
15 14 13
VIN
VCC
SYN
FB
CS−/Vo
CS+
PGND
DL/TRESET
VCCP
BST
DH
SWN
PGOOD
AGND
COMP
IDRP/OCP
NCP5212A/
EN
PGOOD1
EN=VEN_Slave
Slave
Master
Figure 3. Typical Application Circuit (Dual Device Operation)
NCP5212T
NCP5212T
NCP5212A, NCP5212T
http://onsemi.com
5
PIN FUNCTION DESCRIPTION
Pin No. Symbol Description
1 VIN Input voltage used for feed forward in switcher operation.
2 VCC Supply for analog circuit
3 SYN Synchronization interleaving use.
4 EN This pin serves as two functions. Enable: Logic control for enabling the switcher. MASTER/SLAVE: To
program the device as MASTER or SLAVE mode at dual device operation.
5 COMP Output of the error amplifier.
6 FB Output voltage feed back.
7 IDRP/OCP Current limit programmable and setting for AVP.
8 CS−/Vo Inductor current differential sense inverting input.
9 CS+ Inductor current differential sense non−inverting input.
10 PGND Ground reference and high−current return path for the bottom gate driver.
11 DL/TRESET Gate driver output of bottom N−channel MOSFET. It also has the function for TRE threshold setting.
12 VCCP Supply for bottom gate driver.
13 BST Top gate driver input supply, a bootstrap capacitor connection between SWN and this pin.
14 DH Gate driver output of top N−channel MOSFET.
15 SWN Switch node between top MOSFET and bottom MOSFET.
16 PGOOD Power good indicator of the output voltage. High impendence if power good (in regulation). Low im-
pendence if power not good.
17 TPAD Copper pad on bottom of IC used for heat sinking. This pin should be connected to the analog ground
plane under the IC.
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
VCC Power Supply Voltage to AGND V
CC
−0.3, 6.0 V
VIN Supply to AGND V
IN
−0.3, 30 V
High−side Gate Drive Supply: BST to SWN
High−side Gate Drive Voltage: DH to SWN
Low−side Gate Drive Supply: VCCP to PGND
Low−side Gate Drive Voltage: DL to PGND
V
BST
−V
SWN,
V
DH
−V
SWN,
V
CCP
−V
PGND,
V
DL
−V
PGND,
−0.3, 6.0 V
Input / Output Pins to AGND V
IO
−0.3, 6.0 V
Switch Node SWN−PGND V
SWN
−5 V (< 100 ns)
30 V
V
High−Side Gate Drive/Low−Side Gate Drive Outputs DH, DL −3(DC) V
PGND V
PGND
−0.3, 0.3 V
Thermal Characteristics
Thermal Resistance Junction−to−Ambient (QFN16 Package)
R
q
JA
48
°C/W
Operating Junction Temperature Range (Note 1) T
J
−40 to + 150 °C
Operating Ambient Temperature Range T
A
− 40 to + 85 °C
Storage Temperature Range T
stg
− 55 to +150 °C
Moisture Sensitivity Level MSL 1 −
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
1. Internally limited by thermal shutdown, 150°C min.
NCP5212A, NCP5212T
http://onsemi.com
6
ELECTRICAL CHARACTERISTICS (V
IN
= 12 V, V
CC
= V
CCP
= 5 V, T
A
=−40°C to 85°C, unless other noted)
Characteristics
Symbol Test Conditions Min Typ Max Unit
SUPPLY VOLTAGE
Input Voltage
V
IN
4.5 − 27 V
V
CC
Operating Voltage V
CC
4.5 5.0 5.5 V
SUPPLY CURRENT
V
CC
Quiescent Supply Current in
Master operation
IVCC_Master EN = VEN_Master, V
FB
forced above
regulation point. DH, DL are open
1.5 2.5 mA
V
CC
Quiescent Supply Current in
Slave Operation
IVCC_Slave EN = VEN_Slave, V
FB
forced above
regulation point, DH, DL are open
1.5 2.5 mA
V
CC
Shutdown Current IVCC_SD EN = VEN_Disable, V
CC
= 5 V, True
Shutdown
1
mA
BST Quiescent Supply Current in
Master Operation
IBST_Master EN = VEN_Master, V
FB
forced above
regulation point, DH and DL are open,
No boost trap diode
0.3 mA
BST Quiescent Supply Current in
Slave Operation
IBST_Slave EN = VEN_Slave, V
FB
forced above
regulation point, DH and DL are open
No boost trap diode
0.3 mA
BST Shutdown Current IBST_SD EN = 0 V 1
mA
VCCP Shutdown Current IVCCP_SD EN = 0 V, V
CCP
= 5 V 1
mA
VIN Supply Current IVIN EN = 5V, V
IN
= 27 V 35
mA
VIN Shutdown Current IVIN_SD EN = 0 V, V
IN
= 27 V 1
mA
VOLTAGE−MONITOR
Rising VCC Threshold
VCCth+ Wake Up 4.05 4.25 4.48 V
VCC UVLO Hysteresis VCCHYS 200 275 400 mV
Rising VIN Threshold VINth+ Wake Up, Design Spec. (Note 2) 3.4 3.8 4.2 V
VIN UVLO Hysteresis VINHYS (Note 2) 200 500 800 mV
Power Good High Threshold VPGH PGOOD in from
higher Vo
(PGOOD goes
high)
NCP5212A 105 110 115
%
NCP5212T 120 125 130
Power Good High Hysteresis VPGH_HYS PGOOD high hysteresis (PGOOD
goes low)
5 %
Power Good Low Threshold VPGL PGOOD in from lower Vo (PGOOD
goes high)
80 85 90 %
Power Good Low Hysteresis VPGL_HYS PGOOD low hysteresis (PGOOD goes
low)
−5 %
Power Good High Delay Td_PGH After Tss, (Note 2) 1.25 ms
Power Good Low Delay Td_PGL (Note 2) 1.5
ms
Output Overvoltage Rising Threshold OVPth+ With respect to
Error Comparator
Threshold of 0.8 V
NCP5212A 110 115 120
%
NCP5212T 125 130 135
Overvoltage Fault Propagation Delay OVPTblk FB forced 2% above trip threshold
(Note 2)
1.5
ms
Output Undervoltage Trip Threshold UVPth With respect to Error Comparator
Threshold of 0.8 V
75 80 85 %
Output Undervoltage Protection
Blanking Time
UVPTblk (Note 2) − 8/fsw − s
REFERENCE OUTPUT
Internal Reference Voltage
V
ref
0.7936 0.8 0.8064 V
2. Guaranteed by design, not tested in production.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

NCP5212AGEVB

Mfr. #:
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Manufacturer:
ON Semiconductor
Description:
Power Management IC Development Tools NCP5212A EVB
Lifecycle:
New from this manufacturer.
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