MAX530BENG Datasheet MAX530ACAG+, MAX530AEAG+, MAX530AENG+ | P10-P12

An additional 110µA of supply current can be saved

when the internal reference is not used by connecting

REFGND to V

. A low on resistance N-channel FET,

such as the 2N7002, can be used to turn off the internal

reference to create a shutdown mode with minimum

current drain (Figure 3). When CLR is high, the transis-

tor pulls REFGND to AGND and the reference and DAC

operate normally. When CLR goes low, REFGND is

pulled up to V

and the reference is shut down. At the

same time, CLR resets the DAC register to all 0s, and

the op-amp output goes to 0V for unity-gain and G = 2

modes. This reduces the total single-supply operating

current from 250µA (400µA max) to typically 40µA in

shutdown mode.

A small error voltage is added to the reference output

by the reference current flowing through the N-channel

pull-down transistor. The switch’s on resistance should

be less than 5Ω. A typical reference current of 100µA

would add 0.5mV to REFOUT. Since the reference cur-

rent and on resistance increase with temperature, the

overall temperature coefficient will degrade slightly.

As data is loaded into the DAC and the output moves

above GND, the op-amp quiescent current increases to

its nominal value and the total operating current aver-

ages 250µA. Using dual supplies (±5V), the op amp is

fully biased continuously, and the V

supply current is

more constant at 250µA. The V

current is typically

150µA.

The MAX530 logic inputs are compatible with TTL and

CMOS logic levels. However, to achieve the lowest

power dissipation, drive the digital inputs with rail-to-rail

CMOS logic. With TTL logic levels, the power require-

ment increases by a factor of approximately 2.

MAX530

+5V, Low-Power, Parallel-Input,

Voltage-Output, 12-Bit DAC

10 ______________________________________________________________________________________

MAX530

MAX530



12-BIT DAC LATCH

NBL

INPUT

LATCH

NBH

INPUT

LATCH

NBM

INPUT

LATCH

D0/D8

D1/D9

D2/D10

D3/D11

POWER-ON

RESET

CONTROL

LOGIC

DAC

LDAC

CLR

33µF

2.048V

REFERENCE

REFOUT REFIN ROFS

RFB

OUT

+5V

DGND

2N7002

REFGND

AGND

Figure 3. Low-Current Shutdown Mode

A0 A1 DATA UPDATED

L X X X X X Reset DAC Latches

H H X H X X No Operation

H X H H X X No Operation

H L L H H H NBH (D8-D11)

H L L H H L NBM (D4-D7)

H L L H L H NBL (D0-D3)

H H H L X X Update DAC Only

H L L X L L DAC NOT UPDATED

H L L L H H NBH and Update DAC

Table 2. Input Latch Addressing

MAX530

+5V, Low-Power, Parallel-Input,

Voltage-Output, 12-Bit DAC

______________________________________________________________________________________ 11

DATA BITS

(8-BIT BYTE OR

4-BIT NIBBLE)



A0-A1

ADDRESS BUS VALID

AWH

CWS

CWH

AWS

DATA BUS

VALID

NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS

IH +

IL

CLR

LDAC

Figure 4. MAX530 Write-Cycle Timing Diagram

Parallel Logic Interface

Designed to interface with 4-bit, 8-bit, and 16-bit micro-

processors (µPs), the MAX530 uses 8 data pins and

double-buffered logic inputs to load data as 4 + 4 + 4

or 8 + 4. The 12-bit DAC latch is updated simultane-

ously through the control signal LDAC. Signals A0, A1,

WR, and CS select which input latches to update. The

12-bit data is broken down into nibbles (NB); NBL is

the enable signal for the lowest 4 bits, NBM is the

enable for the middle 4 bits, and NBH is the enable for

the highest and most significant 4 bits. Table 2 lists the

address decoding scheme.

Refer to Figure 4 for the MAX530 write-cycle timing

diagram.

Figure 5 shows the circuit configuration for a 4-bit µP

application. Figure 6 shows the corresponding timing

sequence. The 4 low bits (D0-D3) are connected in paral-

lel to the other 4 bits (D4-D7) and then to the µP bus.

Address lines A0 and A1 enable the input data latches

for the high, middle, or low data nibbles. The µP sends

chip select (CS

) and write (WR) signals to latch in each of

three nibbles in three cycles when the data is valid.

Figure 7 shows a typical interface to an 8-bit or a 16-bit

µP. Connect 8 data bits from the data bus to pins D0-D7

on the MAX530. With LDAC

held high, the user can load

NBH or NBL

NBM in any order. Figure 8a shows the

corresponding timing sequence. For fastest throughput,

use Figure 8b’s sequence. Address lines A0 and A1 are

tied together and the DAC is loaded in 2 cycles as 8 + 4.

In this scheme, with LDAC

held low, the DAC latch is

transparent. Always load NBL and NBM first, followed by

NBH.

LDAC

is asynchronous with respect to WR. If LDAC is

brought low before or at the same time WR

goes high,

LDAC

must remain low for at least 50ns to ensure the cor-

rect data is latched. Data is latched into DAC registers on

LDAC

’s rising edge.

MAX530

+5V, Low-Power, Parallel-Input,

Voltage-Output, 12-Bit DAC

12 ______________________________________________________________________________________

A0 = 1, A1 = 1

NBH

NBM

NBL

LDAC

A0 = 1, A1 = 0

A0 = 0, A1 = 1

DAC UPDATE

Figure 6. 4-Bit µP Timing Sequence

A0 = A1 = 1

A0 = A1 = 0

DAC UPDATE

NBH

NBL & NBM

LDAC

Figure 8a. 8-Bit and 16-Bit µP Timing Sequence Using LDAC

Figure 5. 4-Bit µP Interface

DATA BUS

D0-D3 D0-D3

D0-D3

D4-D7

MC6800

FROM

SYSTEM

RESET



R/W

CLR

WR CS

LDAC

DECODER

A0-A15

A13-A15

ADDRESS BUS A0, A1

A0, A1

D0-D3

MAX530

Figure 7. 8-Bit and 16-Bit µP Interface

D0-D7

DATA BUS

D0-D7

MC6809

FROM

SYSTEM

RESET

CLR

A0-A1

CS LDAC

R/W

A0-A15

A13-A15

ADDRESS BUS

DECODER

MAX530

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX530BENG

Mfr. #:

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Manufacturer:

Maxim Integrated

Description:

Digital to Analog Converters - DAC +5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DAC

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