April 2001 3 MIC2596/2597
MIC2596/2597 Micrel
Pin Configuration
1ON1
ILIMIT1
CTIMER1
COL1
VCLAMP
VDD/VDDA*
COL2
CTIMER2
ILIMIT2
ON2
20 FAULT#1
OUT1
N/C
CGATE1
VEE
VDDL*
CGATE2
N/C
OUT2
FAULT#2
19
18
17
16
15
14
13
12
11
2
3
4
5
6
7
8
9
10
20-Pin TSSOP
Pin Descriptions
Pin Number Pin Name Pin Function
20, 11 FAULT1#/FAULT2# Fault Status Output, Active-low - Asserted when the circuit breaker trips
upon overcurrent, open-load or thermal shutdown conditions.
1, 10 ON1/ON2 Enable Input - Active-high (MIC259x-1) or active-low (MIC259x-2). When
asserted ON will initiate a start cycle by activating the GATE output. Tog-
gling ONx will also reset the circuit breaker in the MIC2597.
3, 8 CTIMER1/CTIMER2 Current Limit Response Timer. A capacitor connected to this pin defines the
period of time t
FLT
in which an overcurrent event must last to signal a fault
condition and turn the output off.
16 V
EE
Negative Supply Voltage Input.
2, 9 ILIMIT1/ILIMIT2 Current Limit Set. The current limit threshold is set by connecting a resistor
between this pin and V
EE
. When the current limit threshold of a channel is
exceeded for t
FLT
the circuit breaker for that channel is tripped and its
respective output is immediately shut off.
19, 12 OUT1/OUT2 Switch Outputs. Connect to load.
6 VDDA Positive Supply Input. Normally connected as the power ground reference in
negative supply (–48V) systems. V
DDA
is the IC’s “analog ground,” used for
internal biasing relative to –V
EE
.
5 VCLAMP FAULT# Clamp Voltage. A small bias current into this pin (usually supplied
by the controlling logic’s supply voltage) powers internal circuitry which
establishes the active low voltage of the FAULT# signals. In normal circuit
configurations, the low-level output voltage will be clamped to V
DDL
.
4, 7 COL1/COL2 Open-Load Detect Timer - When the load current falls below 8% of full scale
current limit the capacitor connected to C
OL1
/C
OL2
begins to change. When
the voltage across C
OL1
/C
OL2
rises above 1.32V the output is immediately
shut off. When ONx is deasserted or when the load current is above 15% of
full scale current limit then this pin is held to V
EE
. Tying this pin to V
EE
will
disable this function.
17,14 CGATE1/CGATE2 Noise filtering capacitors for the gates of the main output MOSFETs.
Typically in the range of 1000pF ~ 4700pF.
15 VDDL V
DDL
provides the ground reference for the logic-compatible FAULT# and
ON signals, while accommodating ±8 volts of ground differential between the
controlling logic and the power ground (V
DDA
) of the MIC2596/2597. If no
differential voltage capability is required between V
DDA
and V
DDL
, these two
pins should be tied together at the part.
13, 18 N/C No Connect.
