2
dc1561bf
DEMO MANUAL DC1561B
operating principles
A compatible high power PSE board, such as the DC1567,
connects to the DC1561B at the RJ45 connector J1 (see
the schematic in Figure 12). As required by IEEE 802.3at,
the DC1561B uses a diode bridge across the data pairs
and signal pairs. Schottky diodes (D2-D9) are used at the
input to improve efficiency over standard diode bridges.
The LTC4278 provides the PoE required 25k signature
resistance and classification up to class 4 (25.5W). When
the PD is powered and voltage reaches above the PoE “On
Voltage,” the LTC4278 switches the port voltage over to the
power supply controller through its internal MOSFET. This
voltage allows the Zener and NPN-based linear regulator
(R9/D17/Q3) to power up the bias pin, V
CC
, of the power
supply controller. The IC begins a controlled soft-start of
the output. As the output voltage rises, bias power takes
over by the bias supply made up of T1’s bias winding and
D11 since it reverse biases the linear regulator’s (Q3) base
to emitter junction.
When the soft-start period is over, the output voltage
regulates by observing the pulses across the bias wind-
ing during the flyback time. The Primary Gate drive (PG)
and Synchronous Gate (SG) drive Pulse Width Modulates
(PWM) in order to keep the output voltage constant. The
synchronous gate drive signal transmits to the secondary
via the small signal transformer, T2. The output of T2 drives
a discrete gate drive buffer, R22 and Q6/7 to achieve fast
gate transition times, hence higher efficiency.
The two-stage input filter, C5, L2, and C6 and output filter,
C1/C3, L1, and C9 are the reasons that this PoE flyback
supply has exceptionally low differential mode conducted
emissions. A common mode filter consisting of a common
mode choke (L3) and common mode capacitor (C34) yields
low common mode emissions out of the power supply.
Demonstration circuit 1561B is easy to set up to evaluate
the performance of the LTC4278 in a PoE
+
PD application.
Refer to Figure 1 for proper equipment setup and follow
the procedure below:
1. Place test equipment (voltmeter, ammeter, and electronic
load) across output.
2. Input supplies:
a. Connect a PoE
+
capable PSE, like the DC1567, with
an Ethernet cable to the RJ45 connector, J1. See
Figure 1.
b. Or, connect a 37V to 57V capable power supply
(Power Supply in Figure 1) across VPORT_P and
VPORT_N.
c. Or, if evaluating the auxiliary power supply capa-
bility, connect a 9V to 57V at 4A capable power
supply across AUX+ to AUX– (Auxiliary Supply in
Figure 1).
3. Check for the proper output voltage of 5V.
4. Once the proper output voltage is confirmed, adjust the
output’s load current within the operating range and
observe the output voltage regulation, output ripple
voltage, efficiency, and other parameters.
NOTE: When measuring the input or output voltage ripple,
care must be taken to avoid a long ground lead on the
oscilloscope probe. Measure the output (or input) voltage
ripple by touching the probe tip and probe ground directly
across the +VOUT and –VOUT (or VPORT_P and VPORT_N)
terminals. See Figure 2 for proper scope probe technique.
Quick start proceDure
