AS1702V Datasheet AS1702V, AS1702, AS1702-T | P13-P15

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AS1702 - AS1705

Datasheet - Application Information

BTL Amplifier

All devices are designed to drive loads differentially in a bridge-tied load (BTL) configuration.

Figure 32. Bridge Tied Load Configuration

The BTL configuration doubles the output voltage (illustrated in Figure 32) compared to a single-ended amplifier under similar conditions. Thus,

the differential gain of the device (A

VD) is twice the closed-loop gain of the input amplifier. The effective gain is given by:

Substituting 2 x V

OUT(P-P) for VOUT(P-P) into (EQ 3) and (EQ 4) yields four times the output power due to doubling of the output voltage:

Since the BTL outputs are biased at mid-supply, there is no net DC voltage across the load. This eliminates the need for the large, expensive,

performance degrading DC-blocking capacitors required by single-ended amplifiers.

Power Dissipation and Heat Sinking

Normally, the devices dissipate a significant amount of power. The maximum power dissipation is given in Table 3 as Continuous Power Dissipa-

tion, or it can be calculated by:

where T

J(MAX) is +150ºC, TAMB (see Table 3) is the ambient temperature, and ΘJA is the reciprocal of the derating factor in ºC/W as specified

in Table 3. For example,

ΘJA of the TQFN package is +59.2ºC/W.

The increased power delivered by a BTL configuration results in an increase in internal power dissipation versus a single-ended configuration.

The maximum internal power dissipation for a given V

CC and load is given by:

If the internal power dissipation exceeds the maximum allowed for a given package, power dissipation should be reduced by increasing the

ground plane heat-sinking capabilities and increasing the size of the device traces (see Layout and Grounding Considerations on page 15). Addi-

tionally, reducing V

CC, increasing load impedance, and decreasing ambient temperature can reduce device power dissipation.

-1

VOUT(P-P)

2 x VOUT(P-P)

AVD = 2 x

RIN

(EQ 2)

VRMS =

2 2

(EQ 3)

VOUT(P-P)

POUT =

(EQ 4)

VRMS

PDISSPKF(MAX) =

(EQ 5)

TJ(MAX) -TA

PDISSPKF(MAX) =

(EQ 6)

2VCC

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AS1702 - AS1705

Datasheet - Application Information

The integrated thermal-overload protection circuitry limits the total device power dissipation. Note that if the junction temperature is ≥ +145ºC,

the integrated thermal-overload protection circuitry will disable the amplifier output stage. If the junction temperature is reduced by 9°, the ampli-

fiers will be re-enabled.

Note: A pulsing output under continuous thermal overload results as the device heats and cools.

Fixed Differential Gain (AS1703, AS1704, and AS1705)

The AS1703, AS1704, and AS1705 contain different internally-fixed gains (see Ordering Information on page 19). A fixed gain facilitates simpli-

fied designs, decreased footprint size, and elimination of external gain-setting resistors.

The fixed gain values are achieved using resistors R

1 and R2 (see Figure 31 on page 12).

Adjustable Differential Gain (AS1702)

Gain-Setting Resistors

The AS1702 uses external feedback resistors, RF and RIN (Figure 33), to set the gain of the device as:

where A

V is the desired voltage gain. For example, RIN = 10kΩ, RF = 20kΩ yields a gain of 2V/V, or 6dB.

Note: R

F can be either fixed or variable, allowing the gain to be controlled by software (using a AS150x digital potentiometer. For more infor-

mation on the AS1500 family of digital potentiometers, refer to the latest version of the AS150x data sheet, available from the austria-

microsystems website http://www.austriamicrosystems.com.)

Figure 33. Setting the AS1702 Gain

Input Filter

The BTL inputs can be biased at voltages other than mid-supply. However, the integrated common-mode feedback circuit adjusts for input bias,

ensuring the outputs are still biased at mid-supply. Input capacitors are not required if the common-mode input voltage (VIC) is within the range

specified in Table 4 and Table 5.

AV =

RIN

(EQ 7)

AS1702

–

20kΩ

Bias

Generator

Inverting

Differential Input

Non-Inverting

Differential Input

IN*

10µF

IN*

10µF

RIN

10kΩ

* Optional

CBIAS

0.1µF

OUT+

IN-

OUT-

IN+

BIAS

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AS1702 - AS1705

Datasheet - Application Information

Input capacitor CIN (if used), in conjunction with RIN, forms a high-pass filter that removes the DC bias from an incoming signal. The AC coupling

capacitor allows the amplifier to bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the high-pass filter

is given by:

Setting f

-3dB too high affects the low-frequency response of the amplifier. Capacitors with dielectrics that have low-voltage coefficients such as

tantalum or aluminum electrolytic should be used, since capacitors with high-voltage coefficients, such as ceramics, can increase distortion at

low frequencies.

BIAS Capacitor

BIAS is the output of the internally generated VCC/2 bias voltage. The BIAS bypass capacitor, CBIAS, improves PSRR and THD+N by reducing

power supply noise and other noise sources at the common-mode bias node, and also generates the click- and pop-less DC bias waveform for

the amplifiers. Bypass BIAS with a 0.1µF capacitor to GND. Larger values of C

BIAS (up to 1µF) improve PSRR, but increase tON/tOFF times.

For example, a 1µF C

BIAS capacitor increases tON/tOFF by 10 and improves PSRR by 20dB (at 1kHz).

Note: Do not connect external loads to BIAS.

Supply Bypassing

Proper power supply bypassing – connect a 10µF ceramic capacitor (CBIAS) from VCC to GND – will ensure low-noise, low-distortion perfor-

mance of the device. Additional bulk capacitance can be added as required.

Note: Place C

BIAS as close to the device as possible.

Layout and Grounding Considerations

Well designed PC board layout is essential for optimizing device performance. Use large traces for the power supply inputs and amplifier outputs

to minimize losses due to parasitic trace resistance and route heat away from the device.

Good grounding improves audio performance and prevents digital switching noise from coupling onto the audio signal.

f-3dB =

(EQ 8)

πRINCIN

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