NCV51190MNTAG Datasheet NCP51190MNTAG, NCV51190MNTAG | P1-P3

January, 2017 − Rev. 4

1 Publication Order Number:

NCP51190/D

NCP51190, NCV51190

1.5A DDR Memory

Termination Regulator

The NCP/NCV51190 is a simple, cost−effective, high−speed linear

regulator designed to generate the V

termination voltage rail for

DDR−I, DDR−II and DDR−III memory. The regulator is capable of

actively sourcing or sinking up to ±1.5 A for DDR−I, or up to ±0.5 A

for DDR−II

/−III while regulating the output voltage to within

±30 mV.

The output termination voltage is tightly regulated to track V

DDQ

/ 2) over the entire current range.

The NCP/NCV51190 incorporates a high−speed differential

amplifier to provide ultra−fast response to line and load transients.

Other features include extremely low initial offset voltage, excellent

load regulation, source/sink soft−start and on−chip thermal shut−down

protection.

The NCP/NCV51190 features the power−saving Suspend To Ram

(STR) function which will tri−state the regulator output and lower the

quiescent current drawn when the /SS pin is pulled low.

The NCP/NCV51190 is available in a DFN8 package.

Features

• Generate DDR Memory Termination Voltage (V

)

• For DDR−I, DDR−II, DDR−III Source / Sink Currents

• Supports DDR−I to ±1.5 A, DDR−II, DDR−III to ±0.5 A (peak)

• Integrated Power MOSFETs with Thermal Protection

• Stable with 10 mF Ceramic V

Capacitor

• High Accuracy Output Voltage at Full−Load

• Minimal External Component Count

• Shutdown for Standby or Suspend to RAM (STR) mode

• Built−in Soft Start

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• These are Pb−Free Devices

Appications

• Desktop PC’s, Notebooks, and Workstations

• Graphics Card DDR Memory Termination

• Set Top Boxes, Digital TV’s, Printers

• Embedded Systems

• Active Bus Termination

MARKING

DIAGRAM

www.

onsemi.com

DFN8

MN SUFFIX

CASE 506AA

PIN CONNECTION

XXMG

XX = Specific Device Code

M = Date Code

G = Pb−Free Device

(Note: Microdot may be in either location)

See detailed ordering, marking and shipping information in the

package dimensions section on page 8 of this data sheet.

ORDERING INFORMATION

NCP51190, NCV51190

www.onsemi.com

1.5 A, DDR−I /−II /−III TERMINATION REGULATOR

Figure 1. Typical Application Schematic

PIN FUNCTION DESCRIPTION – NCP51190

Pin Number Pin Name Pin Function

1 PV

The PV

pin provides the rail voltage from where the V

pin draws load current. There is a limitation

between V

and PV

. The PV

voltage must be less or equal to the V

voltage to ensure the

correct output voltage regulation. The V

source current capability is dependent on PV

voltage. The

higher the voltage on PV

, the higher the source current.

2 V

Regulator output voltage capable of sinking and sourcing current while regulating the output rail.

3 GND Common Ground.

4 /SS Suspend Shutdown supports Suspend To RAM function. CMOS compatible input sets V

output to

high impedance state. Logic HI = Enable, Logic LO = Shutdown.

5 V

TTS

is the V

sense input.

6 V

REF

is an output pin that provides the buffered output of the internal reference voltage equal to half of

DDQ

. Two resistors dividing down the V

DDQ

voltage on the pin to create the regulated output voltage.

7 V

DDQ

The V

DDQ

pin is an input pin for creating the internal reference voltage to regulate V

. The V

DDQ

volt-

age is connected to an internal resistor divider. The central tap of resistor divider (V

DDQ

/2) is con-

nected to the internal voltage buffer, which output is connected to V

REF

pin and the non−inverting input

of the error amplifier as the reference voltage.

8 V

Power for the analog control circuitry.

THERMAL

PAD

Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple

vias for maximum power dissipation performance.

NCP51190, NCV51190

www.onsemi.com

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

, PV

DDQ

, /SS to GND (Note 1) −0.3 to +6 V

Storage Temperature T

stg

−65 to +150 °C

Operating Junction Temperature Range T

−40 to +125 °C

Thermal Characteristics, SO8−EP Thermal Resistance, Junction−to−Air

Power Rating at 25°C ambient

TBD °C/W

ESD Capability, Human Body Model (Note 2) ESD

HBM

2000 V

ESD Capability, Machine Model (Note 2) ESD

150 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. No pin to exceed V

. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

2. This device series incorporates ESD protection and is tested by the following method:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)

Latchup Current Maximum Rating tested per JEDEC standard: JESD78.

RECOMMENDED OPERATING CONDITIONS

Rating Symbol Value Unit

Bias Supply Voltage V

2.2 to 5.5 V

Input Voltage PV

1.35 to 2.5 V

Reference Input Voltage V

DDQ

1.35 to 2.7 V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

ELECTRICAL CHARACTERISTICS

−40°C ≤ T

≤ 125°C; V

= PV

= V

DDQ

= 2.5 V; unless otherwise noted. Typical values are at T

= +25°C

Parameter

Condition Symbol Min Typ Max Unit

Reference Voltage (DDR I)

REF

= 0 mA (unloaded)

= V

DDQ

= 2.3 V

= 2.5 V

= 2.7 V

REF

(DDR−I)

1.125

1.225

1.325

1.151

1.251

1.351

1.175

1.275

1.375

Reference Voltage (DDR II)

REF

= 0 mA (unloaded)

= V

DDQ

= 1.7 V

= 1.8 V

= 1.9 V

REF

(DDR−II)

0.830

0.880

0.925

0.851

0.901

0.951

0.880

0.930

0.975

Reference Voltage (DDR III)

REF

= 0 mA (unloaded)

= V

DDQ

= 1.35 V

= 1.5 V

= 1.6 V

REF

(DDR−III)

0.660

0.735

0.785

0.676

0.751

0.801

0.695

0.770

0.820

REF

− Output Impedance

REF

= −30 mA to +30 mA

REF

2.5

Output Voltage

(DDR−I)

OUT

= 0 A

= V

DDQ

= 2.3 V

= V

DDQ

= 2.5 V

= V

DDQ

= 2.7 V

(DDR−I)

−

1.112

1.202

1.312

−

1.150

1.250

1.350

−

1.182

1.282

1.382

OUT

= +1.5 A

= V

DDQ

= 2.3V

= V

DDQ

= 2.5V

= V

DDQ

= 2.7V

(DDR−I)

−

1.115

1.215

1.315

−

1.150

1.250

1.350

−

1.185

1.285

1.385

OUT

= −1.5 A

= V

DDQ

= 2.3V

= V

DDQ

= 2.5V

= V

DDQ

= 2.7V

(DDR−I)

−

1.117

1.217

1.317

−

1.150

1.250

1.350

−

1.182

1.282

1.382

P1-P3 P4-P6 P7-P9

NCV51190MNTAG

Mfr. #:

Buy NCV51190MNTAG

Manufacturer:

ON Semiconductor

Description:

Switching Voltage Regulators 1.5ADDR MEMORY TERML REG

Lifecycle:

New from this manufacturer.

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NCV51190MNTAG

NCV51190MNTAG

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