© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1 Publication Order Number:
MC14175B/D
MC14175B
Quad Type D Flip−Flop
The MC14175B quad type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each of the four flip−flops is positive−edge
triggered by a common clock input (C). An active−low reset input (R)
asynchronously resets all flip−flops. Each flip−flop has independent
Data (D) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flip−flops for
counter and toggle applications.
Features
• Complementary Outputs
• Static Operation
• All Inputs and Outputs Buffered
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Output Compatible with Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load
• Functional Equivalent to TTL 74175
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Parameter
Symbol Value Unit
DC Supply Voltage Range V
DD
−0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V
in
, V
out
−0.5 to V
DD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
I
in
, I
out
± 10 mA
Power Dissipation per Package (Note 1) P
D
500 mW
Ambient Temperature Range T
A
−55 to +125 °C
Storage Temperature Range −65 to +150 °C
Lead Temperature (8−Second Soldering) 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (V
in
or V
out
) v V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Device Package Shipping
†
ORDERING INFORMATION
MC14175BCP PDIP−16 25 Units/Rail
MC14175BD SOIC−16 48 Units/Rail
MC14175BDR2 SOIC−16 2500/Tape & Ree
MC14175BFEL SOEIAJ−16
http://onsemi.com
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
2000/Tape & Ree
MC14175BFELG SOEIAJ−16
(Pb−Free)
2000/Tape & Ree
MC14175BDR2G SOIC−16
(Pb−Free)
2500/Tape & Ree
MC14175BDG SOIC−16
(Pb−Free)
48 Units/Rail
MC14175BCPG PDIP−16
(Pb−Free)
25 Units/Rail
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
1
16
14175BG
AWLYWW
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC14175B
ALYWG
16
1
MC14175BCP
AWLYYWWG
1
1
1
