MAX7030HATJ+ Datasheet MAX7030HATJ+T, MAX7030HATJ+ | P13-P15

MAX7030

Low-Cost, 315MHz and 433.92MHz

ASK Transceiver with Fractional-N PLL

AGC Dwell-Time Settings

The AGC dwell timer holds the AGC in low-gain state

for a set amount of time after the power level drops

below the AGC switching threshold. After that set

amount of time, if the power level is still below the AGC

threshold, the LNA goes into high-gain state. This is

important for ASK since the modulated data may have

a high level above the threshold and low level below

the threshold, which without the dwell timer would

cause the AGC to switch on every bit.

The MAX7030 uses the three AGC control pins (AGC0,

AGC1, AGC2) to set seven user-controlled, dwell-timer

settings. The AGC dwell time is dependent on the crys-

tal frequency and the bit settings of the AGC control

pins. To calculate the dwell time, use the following

equation:

where K is an odd integer in decimal from 11 to 23, deter-

mined by the control pin settings shown in Table 1.

To calculate the value of K, use the following equation

and use the next integer higher than the calculated

result:

K ≥ 3.3 x log

(Dwell Time x f

XTAL

)

For Manchester Code (50% duty cycle), set the dwell

time to at least twice the bit period. For nonreturn-to-

zero (NRZ) data, set the dwell to greater than the peri-

od of the longest string of zeros or ones. For example,

using Manchester Code at 315MHz (f

XTAL

12.679MHz) with a data rate of 2kbps (bit period =

250µs), the dwell time needs to be greater than 500µs:

K ≥ 3.3 x log

(500µs x 12.679) ≈ 12.546

Choose the AGC pin settings for K to be the next odd-

integer value higher than 12.546, which is 13. This says

that AGC1 is set high and AGC0 and AGC2 are set low.

Mixer

A unique feature of the MAX7030 is the integrated

image rejection of the mixer. This eliminates the need

for a costly front-end SAW filter for many applications.

The advantage of not using a SAW filter is increased

sensitivity, simplified antenna matching, less board

space, and lower cost.

The mixer cell is a pair of double-balanced mixers that

perform an IQ downconversion of the RF input to the

10.7MHz intermediate frequency (IF) with low-side

injection (i.e., f

= f

- f

). The image-rejection circuit

then combines these signals to achieve a typical 46dB

of image rejection over the full temperature range. Low-

side injection is required as high-side injection is not

possible due to the on-chip image rejection. The IF out-

put is driven by a source follower, biased to create a

driving impedance of 330Ω to interface with an off-chip

330Ω ceramic IF filter. The voltage-conversion gain dri-

ving a 330Ω load is approximately 20dB. Note that the

MIXIN+ and MIXIN- inputs are functionally identical.

Integer-N Phase-Locked Loop (PLL)

The MAX7030 utilizes a fixed-integer-N PLL to generate

the receive LO. All PLL components, including the loop

filter, voltage-controlled oscillator, charge pump, asyn-

chronous 24x divider, and phase-frequency detector

are integrated internally. The loop bandwidth is approx-

imately 500kHz. The relationship between RF, IF, and

crystal reference frequencies is given by:

XTAL

= (f

- f

)/24

Dwell Time

XTAL

AGC2 AGC1 AGC0 DESCRIPTION

0 0 0 AGC disabled, high gain selected

001

K = 11

010

K = 13

011

K = 15

100

K = 17

101

K = 19

110

K = 21

111

K = 23

Table 1. AGC Dwell Time Settings for

MAX7030

Low-Cost, 315MHz and 433.92MHz

ASK Transceiver with Fractional-N PLL

Intermediate Frequency (IF)

The IF section presents a differential 330Ω load to pro-

vide matching for the off-chip ceramic filter. The internal

six AC-coupled limiting amplifiers produce an overall

gain of approximately 65dB, with a bandpass filter type

response centered near the 10.7MHz IF frequency with

a 3dB bandwidth of approximately 10MHz. For ASK

data, the RSSI circuit demodulates the IF to baseband

by producing a DC output proportional to the log of the

IF signal level with a slope of approximately 15mV/dB.

Data Filter

The data filter for the demodulated data is implemented

as a 2nd-order, lowpass, Sallen-Key filter. The pole

locations are set by the combination of two on-chip

resistors and two external capacitors. Adjusting the

value of the external capacitors changes the corner fre-

quency to optimize for different data rates. Set the cor-

ner frequency in kHz to approximately 3 times the

fastest expected Manchester data rate in kbps from the

transmitter (1.5 times the fastest expected NRZ data

rate). Keeping the corner frequency near the data rate

rejects any noise at higher frequencies, resulting in an

increase in receiver sensitivity.

The configuration shown in Figure 1 can create a

Butterworth or Bessel response. The Butterworth filter

offers a very-flat-amplitude response in the passband

and a rolloff rate of 40dB/decade for the two-pole filter.

The Bessel filter has a linear phase response, which

works well for filtering digital data. To calculate the

value of the capacitors, use the following equations,

along with the coefficients in Table 2:

where f

is the desired 3dB corner frequency.

For example, choose a Butterworth filter response with

a corner frequency of 5kHz:

Choosing standard capacitor values changes C

470pF and C

to 220pF. In the

Typical Application Circuit

and C

are named C16 and C17, respectively.

Data Slicer

The data slicer takes the analog output of the data filter

and converts it to a digital signal. This is achieved by

using a comparator and comparing the analog input to

a threshold voltage. The threshold voltage is set by the

voltage on the DS- pin, which is connected to the nega-

tive input of the data slicer comparator.

Numerous configurations can be used to generate the

data-slicer threshold. For example, the circuit in Figure

2 shows a simple method using only one resistor and

one capacitor. This configuration averages the analog

output of the filter and sets the threshold to approxi-

mately 50% of that amplitude. With this configuration,

the threshold automatically adjusts as the analog signal

varies, minimizing the possibility for errors in the digital

data. The values of R and C affect how fast the thresh-

old tracks the analog amplitude. Be sure to keep the

corner frequency of the RC circuit much lower (about

10 times) than the lowest expected data rate.

With this configuration, a long string of NRZ zeros or

ones can cause the threshold to drift. This configuration

works best if a coding scheme, such as Manchester

coding, which has an equal number of zeros and ones,

is used.

Figure 3 shows a configuration that uses the positive and

negative peak detectors to generate the threshold. This

configuration sets the threshold to the midpoint between

a high output and a low output of the data filter.

k kHz

1 000

1 414 100 3 14 5

450

1 414

4 100 3 14 5

225

=≈

( . )( )( . )( )

( )( )( . )( )

ak f

100

4 100

()()()

MAX7030

RSSI

100kΩ

DFOP+DS+

Figure 1. Sallen-Key Lowpass Data Filter

FILTER TYPE a b

Butterworth

(Q = 0.707)

1.414 1.000

Bessel

(Q = 0.577)

1.3617 0.618

Table 2. Coefficients to Calculate C

and

MAX7030

Low-Cost, 315MHz and 433.92MHz

ASK Transceiver with Fractional-N PLL

Peak Detectors

The maximum peak detector (PDMAX) and minimum

peak detector (PDMIN), with resistors and capacitors

shown in Figure 3, create DC output voltages equal to

the high- and low-peak values of the filtered demodulat-

ed signal. The resistors provide a path for the capaci-

tors to discharge, allowing the peak detectors to

dynamically follow peak changes of the data filter out-

put voltages.

The maximum and minimum peak detectors can be

used together to form a data slicer threshold voltage at

a value midway between the maximum and minimum

voltage levels of the data stream (see the

Data Slicer

section and Figure 3). Set the RC time constant of the

peak detector combining network to at least 5 times the

data period.

If there is an event that causes a significant change in

the magnitude of the baseband signal, such as an AGC

gain-switch or a power-up transient, the peak detectors

may “catch” a false level. If a false peak is detected, the

slicing level is incorrect. The MAX7030 peak detectors

correct these problems by temporarily tracking the

incoming baseband filter voltage when an AGC state

switch occurs, or forcing the peak detectors to track the

baseband filter output voltage until all internal circuits are

stable following an enable pin low-to-high transition and

also T/R pin high-to-low transition. The peak detectors

exhibit a fast attack/slow decay response. This feature

allows for an extremely fast startup or AGC recovery.

Transmitter

Power Amplifier (PA)

The PA of the MAX7030 is a high-efficiency, open-

drain, switch-mode amplifier. The PA with proper

output-matching network can drive a wide range of

antenna impedances, which includes a small-loop PCB

trace and a 50Ω antenna. The output-matching network

for a 50Ω antenna is shown in the

Typical Application

Circuit

. The output-matching network suppresses the

carrier harmonics and transforms the antenna imped-

ance to an optimal impedance at PAOUT (pin 5). The

optimal impedance at PAOUT is between 100Ω and

150Ω to transmit +10dBm with a 2.7V supply.

When the output-matching network is properly tuned,

the PA transmits power with a high overall efficiency of

up to 32%. The efficiency of the PA itself is more than

46%. The output power is set by an external resistor at

PAOUT and is also dependent on the external antenna

and antenna-matching network at the PA output.

Envelope Shaping

The MAX7030 features an internal envelope-shaping

resistor, which connects between the open-drain output

of the PA and the power supply (see the

Typical

Application Circuit

). The envelope-shaping resistor

slows the turn-on/turn-off of the PA in ASK mode and

results in a smaller spectral width of the modulated PA

output signal.

Fractional-N Phase-Locked Loop (PLL)

The MAX7030 utilizes a fully integrated, fractional-N,

PLL for its transmit frequency synthesizer. All PLL com-

ponents, including the loop filter, are integrated inter-

nally. The loop bandwidth is approximately 200kHz.

Power-Supply Connections

The MAX7030 can be powered from a 2.1V to 3.6V sup-

ply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply is

used, then the on-chip linear regulator reduces the 5V

supply to the 3V needed to operate the chip.

To operate the MAX7030 from a 3V supply, connect

PAVDD, AVDD, DVDD, and HVIN to the 3V supply.

When using a 5V supply, connect the supply to HVIN

MAX7030

PDMAX PDMIN

DATA

SLICER

DATA

PEAK

DET

PEAK

DET

Figure 3. Generating Data-Slicer Threshold Using the Peak

Detectors

MAX7030

DS- DS+

DATA

SLICER

DATA

Figure 2. Generating Data-Slicer Threshold Using a Lowpass

Filter

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

MAX7030HATJ+

Mfr. #:

Buy MAX7030HATJ+

Manufacturer:

Maxim Integrated

Description:

RF Transceiver 315/345/433.92MHz ASK Transceiver

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MAX7030HATJ+

MAX7030HATJ+

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