1. General description
The 74LVC2952A is a high-performance, low power, low voltage, Si-gate CMOS device
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 V
and 5 V environment.
The 74LVC2952A is an octal non-inverting registered transceiver. Two 8-bit back-to-back
registers store data flowing in both directions between two bidirectional buses. Data
applied to the inputs is entered and stored on the rising edge of the clock (CPAB, CPBA)
provided that the clock enable (CEAB, CEBA) input is LOW. The data is then present at
the 3-state output buffers, but is only accessible when the output enable (OEAB, OEBA)
input is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.
2. Features
■ 5 V tolerant inputs/outputs for interfacing with 5 V logic
■ Supply voltage range from 1.2 V to 3.6 V
■ CMOS low-power consumption
■ Direct interface with TTL levels
■ Inputs accept voltages up to 5.5 V
■ Flow-through pin-out architecture
■ Complies with JEDEC standard JESD8-B/JESD36
■ ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ Specified from −40 °Cto+85°C and from −40 °C to +125 °C.
74LVC2952A
Octal registered transceiver with 5 V tolerant inputs/outputs;
3-state
Rev. 02 — 29 June 2004 Product data sheet
