9397 750 13251 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 29 June 2004 4 of 19
Philips Semiconductors
74LVC2952A
Octal registered transceiver
6. Pinning information
6.1 Pinning
Fig 2. Logic symbol. Fig 3. IEC logic symbol.
001aab024
CPBA
B0
OEBA CEBA
B1
B2
B3
B4
B5
B6
OEAB
10
16
15 13
17
18
19
20
21
22
14
8
9
7
6
5
4
3
2
11
B7
CPAB
A0
A1
A2
A3
A4
A5
A6
A7
23
1
CEAB
1C5
EN4
2C6
EN3
8
7
16
17
001aab025
4
3
9
15
14
10
G1
G2
13
11
5D1
1
6D
6
18
5
19
4
20
3
21
2
22
1
23
Fig 4. Pin configuration.
2952A
B7 V
CC
B6 A7
B5 A6
B4 A5
B3 A4
B2 A3
B1 A2
B0 A1
OEAB A0
CPAB OEBA
CEAB CPBA
GND CEBA
001aab027
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
9397 750 13251 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 29 June 2004 5 of 19
Philips Semiconductors
74LVC2952A
Octal registered transceiver
6.2 Pin description
Table 3: Pin description
Symbol Pin Description
B7 1 B data input/output
B6 2 B data input/output
B5 3 B data input/output
B4 4 B data input/output
B3 5 B data input/output
B2 6 B data input/output
B1 7 B data input/output
B0 8 B data input/output
OEAB 9 A to B output enable input (active LOW)
CPAB 10 A to B clock input (LOW-to-HIGH, edge-triggered)
CEAB 11 A to B clock enable input (active LOW)
GND 12 ground (0 V)
CEBA 13 B to A clock enable input (active LOW)
CPBA 14 B to A clock input (LOW-to-HIGH, edge-triggered)
OEBA 15 B to A output enable input (active LOW)
A0 16 A data input/output
A1 17 A data input/output
A2 18 A data input/output
A3 19 A data input/output
A4 20 A data input/output
A5 21 A data input/output
A6 22 A data input/output
A7 23 A data input/output
V
CC
24 supply voltage
9397 750 13251 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 29 June 2004 6 of 19
Philips Semiconductors
74LVC2952A
Octal registered transceiver
7. Functional description
7.1 Function table
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state;
NC = no change;
X = don’t care;
= LOW-to-HIGH level transition.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO24 packages: above 70 °C the value of P
tot
derates linearly with 5.5 mW/K.
For T(SSOP)24 packages: above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
Table 4: Function table for register An or Bn
[1]
Operating mode Input Internal latch
An or Bn CPxx CExx
Hold data X X H NC
Load data L LL
Load data H LH
Table 5: Function table for output enable
[1]
Operating mode Input OExx Internal latch Output An or Bn
Disable outputs H X Z
Enable outputs L L L
Enable outputs L H H
Table 6: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +6.5 V
I
IK
input diode current V
I
<0V - 50 mA
V
I
input voltage
[1]
0.5 +6.5 V
I
OK
output diode current V
O
>V
CC
or V
O
<0V - ±50 mA
V
O
output voltage output HIGH or LOW state
[1]
0.5 V
CC
+ 0.5 V
output 3-state
[1]
0.5 +6.5 V
I
O
output source or sink current V
O
= 0 V to V
CC
- ±50 mA
I
CC
,I
GND
V
CC
or GND current - ±100 mA
T
stg
storage temperature 65 +150 °C
P
tot
power dissipation T
amb
= 40 °C to +125 °C
[2]
- 500 mW

74LVC2952APW,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Bus Transceivers 3.3V OCTAL REG. BUS
Lifecycle:
New from this manufacturer.
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