74F673APC

© 2000 Fairchild Semiconductor Corporation DS009585 www.fairchildsemi.com
April 1988
Revised October 2000
74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register
74F673A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 74F673A contains a 16-bit serial-in, serial-out shift
register and a 16-bit Parallel-Out storage register. A single
pin serves either as an input for serial entry or as a
3-STATE serial output. In the Serial-Out mode, the data
recirculates in the shift register. By means of a separate
clock, the contents of the shift register are transferred to
the storage register for parallel outputting. The contents of
the storage register can also be parallel loaded back into
the shift register. A HIGH signal on the Chip Select input
prevents both shifting and parallel transfer. The storage
register may be cleared via STMR
.
Features
Serial-to-parallel converter
16-bit serial I/O shift register
16-bit parallel-out storage register
Recirculating serial shifting
Recirculating parallel transfer
Common serial data I/O pin
Slim 24 lead package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F673ASC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F673APC N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
74F673ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F673A
Unit Loading/Fan Out
Functional Description
The 16-bit shift register operates in one of four modes, as
indicated in the Shift Register Operations Table. A HIGH
signal on the Chip Select (CS
) input prevents clocking and
forces the Serial Input/Output (SI/O) 3-STATE buffer into
the high impedance state. During serial shift-out opera-
tions, the SI/O buffer is active (i.e., enabled) and the output
data is also recirculated back into the shift register. When
parallel loading the shift register from the storage register,
serial shifting is inhibited.
The storage register has an asynchronous master reset
(STMR
) input that overrides all other inputs and forces the
Q
0
Q
15
outputs LOW. The storage register is in the Hold
mode when either CS
or the Read/Write (R/W) input is
HIGH. With CS
and R/W both LOW, the storage register is
parallel loaded from the shift register.
Shift Register Operations Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Transition
Storage Register Operations Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
CS Chip Select Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
SHCP
Shift Clock Pulse Input (Active Falling Edge) 1.0/1.0 20 µA/0.6 mA
STMR
Store Master Reset Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
STCP Store Clock Pulse Input 1.0/1.0 20
µA/0.6 mA
R/W
Read/Write Input 1.0/1.0 20 µA/0.6 mA
SI/O Serial Data Input or 3.5/1.0 70
µA/0.6 mA
3-STATE Serial Output 150/40
3 mA/24 mA
Q
0
Q
15
Parallel Data Outputs 50/33.3 1 mA/20 mA
Control Inputs SI/O
Operating Mode
CS
R/W SHCP STCP Status
H X X X High Z Hold
L L X Data In Serial Load
LH
L Data Out Serial Output
with Recirculation
LH
H Active Parallel Load;
No Shifting
Control Inputs Operating
STMR
CS R/W STCP Mode
L X X X Reset; Outputs LOW
H H X X Hold
HXHXHold
HLL
Parallel Load
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74F673A
Block Diagram

74F673APC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Counter Shift Registers 16-Bit Shft Register
Lifecycle:
New from this manufacturer.
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