IRDC3048
7
Rev. 1.1
06/03/02
www.irf.com
Figure 9 - Gate signals for 3.3V output.
Ch1: Output current 2A/div.
Ch2: Gate signal for control FET 20V/div.
Ch3: Gate signal for sync FET 10V/div.
Figure 11 - Gate signals for 1.8V output.
Ch1: Output current 2A/div.
Ch2: Gate signal for control FET 10V/div.
Ch3: Gate signal for sync FET 10V/div.
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Data and specifications subject to change without notice. 7/25/2002
TEST DATA
Figure 8 - Output voltage ripple for 1.8V @ 4A.
Figure 10 - Soft-start voltage Vs. output voltages.
VOUT1: 3.3V
VOUT2: 1.8V
VOUT3: 2.5V
Vss
