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CY2DP814ZXI

P1-P3P4-P6P7-P9P10-P12P13-P15
CY2DP814
1:4 Clock Fanout Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-07060 Rev. *J Revised December 4, 2014
1:4 Clock Fanout Buffer
Features
■ Low-voltage operation
■ V
DD
= 3.3 V
■ 1:4 fanout
■ Single input configurable for LVDS, LVPECL, or LVTTL
■ Four differential pairs of LVPECL outputs
■ Drives 50-ohm load
■ Low input capacitance
■ Less than 4 ns typical propagation delay
■ 85 ps typical output-to-output skew
■ Commercial temperature range
■ Available in TSSOP package
Description
The Cypress CY2 series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DP814 fanout buffer features a single LVDS-
or a single LVPECL-compatible input and four LVPECL output
pairs.
Designed for data communications clock management
applications, the fanout from a single input reduces loading on
the input clock.
The CY2DP814 is ideal for both level translations from
single-ended to LVPECL, and/or for the distribution of
LVDS-based clock signals. The Cypress CY2DP814 has
configurable input between logic families. The input can be
selectable for an LVPECL, LVTTL or LVDS signal, while the
output drivers support LVPECL capable of driving 50-ohm lines.
For a complete list of related documentation, click here.
Logic Block Diagram
OUTPUT
IN+ 6
IN- 7
16 Q1A
15 Q1B
14 Q2A
13 Q2B
10 Q4A
9 Q4B
12 Q3A
11 Q3B
LVDS /
LVPECL /
LVTTL
CONFIG 2
EN1 1
EN2 8
LVPECL
CY2DP814
Document Number: 38-07060 Rev. *J Page 2 of 15
Contents
Pin Configuration .............................................................3
Pin Description .................................................................3
EN1 EN2 Function Table ..................................................4
Input Receiver Configuration ..........................................4
Function Control of the TTL Input Logic ........................5
Power Supply Characteristics .........................................5
Maximum Ratings .............................................................8
DC Electrical Characteristics ..........................................8
DC Electrical Characteristics ..........................................8
DC Electrical Characteristics ..........................................9
DC Electrical Characteristics ..........................................9
AC Switching Characteristics .......................................10
High-frequency Parametrics ..........................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Drawing and Dimensions ...............................12
Acronyms ........................................................................13
Document Conventions .................................................13
Units of Measure .......................................................13
Document History Page .................................................14
Sales, Solutions, and Legal Information ......................15
Worldwide Sales and Design Support ....................... 15
Products ....................................................................15
PSoC® Solutions ......................................................15
Cypress Developer Community .................................15
Technical Support .....................................................15
CY2DP814
Document Number: 38-07060 Rev. *J Page 3 of 15
Pin Configuration
Figure 1. 16-pin TSSOP/SOIC pinout
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
CY2DP814
16 pin TSSOP / SOIC
EN1
CONFIG
VDD
VDD
IN+
IN-
EN2
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Pin Description
Pin Number Pin Name Pin Standard Interface Description
6, 7 IN+, IN Configurable Differential input pair or single line. LVPECL default. See CONFIG below.
2 CONFIG LVTTL/LVCMOS Converts inputs from the default LVPECL/LVDS (logic = 0) to
LVTTL/LVCMOS (logic = 1).
See Figure 2 on page 4 and Figure 3 on page 4 for additional information.
1, 8 EN1, EN2 LVTTL/LVCMOS Enable/disable logic. See Function Table below for details.
16, 15, 14, 13,
12, 11, 10, 9
Q1A, Q1B,
Q2A, Q2B,
Q3A, Q3B,
Q4A, Q4B
LVPECL Differential outputs.
3, 4 V
DD
POWER Positive supply voltage.
5 GND POWER Ground.
P1-P3P4-P6P7-P9P10-P12P13-P15

CY2DP814ZXI

Mfr. #:
Buy CY2DP814ZXI
Manufacturer:
Cypress Semiconductor
Description:
IC CLK BUFFER 1:4 450MHZ 16TSSOP
Lifecycle:
New from this manufacturer.
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