DS1868B
DESCRIPTION
The DS1868B Dual Digital Potentiometer Chip consists of two digitally controlled solid-state
potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section
and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the
wiper on the resistor array is set by an 8-bit value that controls which tap point is connected to the wiper
output. Communication and control of the device is accomplished via a 3-wire serial port interface. This
interface allows the device wiper position to be read or written.
Both potentiometers can be connected in series (or stacked) for an increased total resistance with the same
resolution. For multiple-device, single-processor environments, the DS1868B can be cascaded or daisy
chained. This feature provides for control of multiple devices over a single 3-wire bus.
The DS1868B is offered in three standard resistance values which include 10kΩ, 50kΩ, and 100kΩ
versions. The part is available in 16-pin SO (300-mil) and 20-pin (173-mil) TSSOP packages.
OPERATION
The DS1868B contains two 256-position potentiometers whose wiper positions are set by an 8-bit value.
These two 8-bit values are written to a 17-bit I/O shift register which is used to store the two wiper
positions and the stack select bit when the device is powered. A block diagram of the DS1868B is
presented in Figure 1.
Communication and control of the DS1868B is accomplished through a 3-wire serial port interface that
drives an internal control logic unit. The 3-wire serial interface consists of the three input signals:
,
CLK, and DQ.
The
control signal is used to enable the 3-wire serial port operation of the device. The
signal is
an active-high input and is required to begin any communication to the DS1868B. The CLK signal input
is used to provide timing synchronization for data input and output. The DQ signal line is used to transmit
potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the
DS1868B.
Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the
signal input is low. Communication with the DS1868B requires the transition of the
input from a
low state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low
to high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the
timing diagrams of Figure 9(b),(c).
Data written to the DS1868B over the 3-wire serial interface is stored in the 17-bit I/O shift register (see
Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the
stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift
register contains the stack select bit. This bit will be discussed in the section entitled Stacked
Configuration. Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value.
Bit 1 will contain the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper
setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position
with the MSB for the wiper position occupying bit 9 and the LSB bit 16.
Maxim Integrated ............................................................................................................................................................................................. 2
