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DS1868BS-100+T/R

P1-P3P4-P6P7-P9P10-P12P13-P13
DS1868B
STACKED CONFIGURATION Figure 3
CASCADE OPERATION
A feature of the DS1868B is the ability to control multiple devices from a single processor. Multiple
DS1868Bs can be linked or daisy-chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1868B a bit will appear at the C
OUT
output after a minimum delay of 50ns. The stack
select bit of the DS1868B will always be the first out of the part at the beginning of a transaction. The
C
OUT
pin will always have the value of the stack select bit (b0) when
RST
is inactive.
CASCADING MULTIPLE DEVICES Figure 4
The C
OUT
output of the DS1868B can be used to drive the DQ input of another DS1868B. When
connecting multiple devices, the total number of bits transmitted is always 17 times the number of
DS1868Bs in the daisy chain.
An optional feedback resistor can be placed between the C
OUT
terminal of the last device and the first
DS1868B DQ, input thus allowing the controlling processor to read, as well as, write data, or circularly
clock data through the daisy chain. The value of the feedback or isolation resistor should be in the range
from 2Ω to 10kΩ.
When reading data via the C
OUT
pin and isolation resistor, the DQ line is left floating by the reading
device. When
RST
is driven high, bit 17 is present on the C
OUT
pin, which is fed back to the input DQ pin
through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the first
position of the I/O shift register and bit 16 becomes present on C
OUT
and DQ of the next device. After 17
bits (or 17 times the number of DS1868Bs in the daisy chain), the data has shifted completely around and
back to its original position. When
RST
transitions to the low state to end data transfer, the value (the
same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register.
Maxim Integrated ............................................................................................................................................................................................. 4
DS1868B
ABSOLUTE AND RELATIVE LINEARITY
Absolute linearity, also known as Integral Nonlinearity, is defined as the difference between the actual
measured output voltage and the expected output voltage. Figure 5 presents the test circuit used to
measure absolute linearity. Absolute linearity is given in terms of a minimum increment or expected
output when the wiper is moved one position. In the case of the test circuit, a minimum increment (MI) or
one LSB would equal 5/256V. The equation for absolute linearity is given as follows:
(1) ABSOLUTE LINEARITY (INL)
AL={V
O
(actual) - V
O
(expected)}/MI
Relative linearity, also known as Differential Nonlinearity, is a measure of error between two adjacent
wiper position points and is given in terms of MI by equation (2).
(2) RELATIVE LINEARITY (DNL)
RL={V
O
(n+1) - V
O
(n)}/MI
Figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the DS1868B at
25°C. The specification for absolute linearity of the DS1868B is ±0.75 MI typical. The specification for
relative linearity of the DS1868B is ±0.3 MI typical.
LINEARITY MEASUREMENT CONFIGURATION Figure 5
Maxim Integrated ............................................................................................................................................................................................. 5
DS1868B
DS1868B ABSOLUTE AND RELATIVE LINEARITY Figure 6
TYPICAL APPLICATION CONFIGURATIONS
Figures 7 and 8 show two typical application configurations for the DS1868B. By connecting the wiper
terminal of the part to a high-impedance load, the effects of the wiper resistance is minimized, since the
wiper resistance can vary from 900Ω to 2000Ω, depending on wiper voltage. Figure 7 presents the device
connected in a variable gain amplifier. The gain of the circuit on Figure 7 is given by the following
equation:
A
V
=
n-256
256 +
where n = 0 to 255
Figure 8 shows the device operating in a fixed gain attenuator where the potentiometer is used to
attenuate an incoming signal. Note the resistance R1 is chosen to be much greater than the wiper
resistance to minimize its effect on circuit gain.
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 32 64 96 128 160 192 224 256
LSB
Tap Position
Linearity vs. Tap Position
INL
DNL
DS1868B
10kΩ
Maxim Integrated ............................................................................................................................................................................................. 6
P1-P3P4-P6P7-P9P10-P12P13-P13

DS1868BS-100+T/R

Mfr. #:
Buy DS1868BS-100+T/R
Manufacturer:
Maxim Integrated
Description:
Digital Potentiometer ICs Dual 256-step digital potentiometer, 100k ohm end to end resistance
Lifecycle:
New from this manufacturer.
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