Data Sheet ADG1411/ADG1412/ADG1413
Rev. C | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1
1
D1
2
S1
3
V
SS
4
IN2
16
D2
15
S2
14
V
DD
13
GND
5
NIC
12
S4
6
S3
11
D4
7
D3
10
IN4
8
IN3
9
NOTES
1. NIC = NO INTERNAL CONNECTION.
ADG1411/
ADG1412/
ADG1413
TOP VIEW
(Not to Scale)
06815-002
Figure 2. TSSOP Pin Configuration
06815-003
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. TIE THE EXPOSED PAD TO THE SUBSTRATE, V
SS
.
12
11
10
1
3
4
9
2
6
5
7
8
16
15
14
13
S1
V
SS
GND
S4
S2
D2
IN2
IN1
D1
V
DD
NIC
S3
D4
IN4
IN3
D3
TOP VIEW
(Not to Scale)
ADG1411/
ADG1412/
ADG1413
Figure 3. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 15 IN1 Logic Control Input.
2 16 D1 Drain Terminal. This pin can be an input or output.
3 1 S1 Source Terminal. This pin can be an input or output.
4 2 V
SS
Most Negative Power Supply Potential.
5 3 GND Ground (0 V) Reference.
6 4 S4 Source Terminal. This pin can be an input or output.
7 5 D4 Drain Terminal. This pin can be an input or output.
8 6 IN4 Logic Control Input.
9 7 IN3 Logic Control Input.
10 8 D3 Drain Terminal. This pin can be an input or output.
11 9 S3 Source Terminal. This pin can be an input or output.
12 10 NIC No Internal Connection.
13 11 V
DD
Most Positive Power Supply Potential.
14 12 S2 Source Terminal. This pin can be an input or output.
15 13 D2 Drain Terminal. This pin can be an input or output.
16 14 IN2 Logic Control Input.
N/A
1
0 EPAD Exposed Pad. Tie the exposed pad to the substrate, V
SS
.
1
N/A means not applicable.
Table 6. ADG1411/ADG1412 Truth Table
ADG1411 INx ADG1412 INx Switch Condition
0 1 On
1 0 Off
Table 7. ADG1413 Truth Table
ADG1413 INx S1, S4 S2, S3
0 Off On
1 On Off