9
FN6486.2
September 8, 2015
Functional Pin Description
SYMBOL FUNCTION
SDA Bidirectional data from/to I
2
C bus.
SCL Clock from I
2
C bus.
VSW1, VSW2 Input of the linear post-regulator.
PGND1, PGND2 Dedicated ground for the output gate driver of respective PWM.
CS1, CS2 Current sense input; connect the sense resistor R
SC
at this pin for desired overcurrent value for respective PWM.
SGND Small signal ground for the IC.
TCAP1, TCAP2 Capacitor for setting rise and fall time of the output of LNB A and LNB B respectively. Typical value is 0.15µF.
BYPASS Bypass capacitor for internal 5V.
TXT1, TXT2 TXT1 and TXT2 are the Tone Transmit signal inputs used to change the tone decoder threshold. The threshold is 200mV max
for the Rx mode. The TXT1, TXT2 are set low and the threshold is 400mV min in the Tx mode when TXT1, TXT2 are set high.
VCC Main power supply to the chip.
GATE1, GATE2 These are the gate drive outputs of PWM A and PWM B respectively. These high current driver outputs are capable of driving
the gate of a power FET. These outputs are actively held low when V
CC
is below the UVLO threshold.
VO1, VO2 Output voltage for LNB A and LNB B respectively.
ADDR0, ADDR1 Address pins select four different device addresses per Table 19.
EXTM1, EXTM2 These pins can be used in two ways :
1) As an input for externally modulated DiSEqC tone signal which is transfered to the symetrically onto V
OUT
2) Alternatively apply a DiSEqC modulation envelope which modulates an internal tone and then transfers it symetrically onto
V
OUT
FLT This is an open drain output from the controller. When the FLT goes low it indicates that an Over-Temperature, Over Load
Fault, UVLO, or a condition causing I
2
C to reset has occured. The processor should then look at the I
2
C register to get the
actual cause of the error. A high on the FLT
indicates that the device is functioning normally.
CPVOUT Charge pump decoupling capacitor is to be connected to this pin.
SELVTOP1,
SELVTOP2
When this pin is low, the V
OUT
is in the 13.3V/14.3V range selected by the I
2
C bit VBOT1 and VBOT2.
When this pin is high, the 18.3V/19.3V range is selected by the I
2
C bit VTOP1 and VTOP2.
The voltage select pin voltage VSPEN1, VSPEN2 I
2
C bit must be set low for the SELVTOP1, SELVTOP2 pins to be active.
Setting VSPEN1, VSPEN2 high disables these pins and voltage selection will be done using the I
2
C bits VBOT1, VBOT2 and
VTOP1, VTOP2 only.
TDIN1, TDIN2,
TDOUT1, TDOUT2
TDIN1, TDIN2 are the tone decoder inputs for Channels 1 and 2. TDOUT1, TDOUT2 are the tone detector outputs for Channels
1 and 2. TDOUT1, TDOUT2 are open drain outputs.
ISL6422B
