LTC4095
13
4095fa
APPLICATIONS INFORMATION
Figure 6. USB Soft Connect Circuit
charge currents, the LTC4095 power dissipation is
approximately:
P
D
= (IN – BAT) • I
BAT
where P
D
is the power dissipated, IN is the input supply
voltage, BAT is the battery voltage and I
BAT
is the charge
current. It is not necessary to perform any worst-case
power dissipation scenarios because the LTC4095 will
automatically reduce the charge current to maintain the
die temperature at approximately 115°C. However, the
approximate ambient temperature at which the thermal
feedback begins to protect the IC is:
T
A
= 115°C – P
D
θ
JA
T
A
= 115°C – (IN – BAT) • I
BAT
θ
JA
Example: Consider an LTC4095 operating from a USB port
providing 500mA to a 3.5V Li-Ion battery. The ambient
temperature above which the LTC4095 will begin to reduce
the 500mA charge current is approximately:
T
A
= 115°C – (5V – 3.5V) • (500mA) • 60°C/W
T
A
= 115°C – 0.75W • 60°C/W = 115°C – 45°C
T
A
= 70°C
The LTC4095 can be used above 70°C, but the charge cur-
rent will be reduced from 500mA. The approximate current
at a given ambient temperature can be calculated:
I
CT
IN BAT
BAT
A
JA
=
°
()
115
–•θ
Using the previous example with an ambient temperature of
88°C, the charge current will be reduced to approximately:
I
CC
VV CW
C
CA
BAT
=
°°
()
°
=
°
°
=
115 88
535 60
27
90
–. • / /
3300mA
Furthermore, the voltage at the PROG pin will change
proportionally with the charge current as discussed in
the Programming Charge Current section.
It is important to remember that LTC4095 applications do
not need to be designed for worst-case thermal conditions
since the IC will automatically reduce power dissipation
when the junction temperature reaches approximately
115°C.
USB Inrush Limiting
When a USB cable is plugged into a portable product,
the inductance of the cable and the high-Q ceramic input
capacitor form an L-C resonant circuit. If there is not
much impedance in the cable, it is possible for the voltage
at the input of the product to reach as high as twice the
USB voltage (~10V) before it settles out. In fact, due to
the high voltage coeffi cient of many ceramic capacitors (a
nonlinearity), the voltage may even exceed twice the USB
voltage. To prevent excessive voltage from damaging the
LTC4095 during a hot insertion, the soft connect circuit
in Figure 6 can be employed.
In this circuit, capacitor C2 holds MN1 off when the cable
is fi rst connected. Eventually C2 begins to charge up to
the USB input voltage applying increasing gate support
to MN1. The long time constant of R1 and C1 prevent
the current from building up in the cable too fast thus
dampening out any resonant overshoot.
LTC4095
USB CABLE
IN
GND
C1
10µF
C2
100nF
4095 F06
MN1
Si2302
R1
40k
8
2
5V
USB
INPUT
Battery Charger Stability Considerations
The LTC4095’s battery charger contains both a constant-
voltage and a constant-current control loop. The constant-
voltage loop is stable without any compensation when a
battery is connected with low impedance leads. Excessive
lead length, however, may add enough series inductance
to require a bypass capacitor of at least 1µF from BAT to
GND. Furthermore, a 4.7µF capacitor in series with a 0.2Ω
to 1Ω resistor from BAT to GND is required to keep ripple
voltage low when the battery is disconnected.
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22µF may
be used in parallel with a battery, but larger ceramics should
be decoupled with 0.2Ω to 1Ω of series resistance.
LTC4095
14
4095fa
APPLICATIONS INFORMATION
In constant-current mode, the PROG pin is in the feed-
back loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the battery
charger is stable with program resistor values as high
as 25k. However, additional capacitance on this node
reduces the maximum allowed program resistor. The pole
frequency at the PROG pin should be kept above 100kHz.
Therefore, if the PROG pin has a parasitic capacitance,
C
PROG
, the following equation should be used to calculate
the maximum resistance value for R
PROG
:
R
C
PROG
PROG
1
210
5
π ••
The stability of the constant-current loop also needs to
be considered when average, rather than instantaneous,
battery current is of interest to the user. For example, if a
switching power supply operating in low current mode is
connected in parallel with the battery, the average current
being pulled out of the BAT pin is typically of more interest
than the instantaneous current pulses. In such a case, a
simple RC fi lter an be used on the PROG pin to measure
the average battery current as shown in Figure 7. A 10k
resistor has been added between the PROG pin and the
lter capacitor to ensure stability.
Board Layout Considerations
In order to deliver maximum charge current under all
conditions, it is critical that the exposed metal pad on
the backside of the LTC4095 package is soldered to the
PC board ground. Correctly soldered to a 2500mm
2
double-sided 1oz. copper board the LTC4095 has a ther-
mal resistance of approximately 60°C/W. Failure to make
thermal contact between the Exposed Pad on the backside
of the package and the copper board will result in thermal
resistances far greater than 60°C/W. As an example, a
correctly soldered LTC4095 can deliver over 950mA to a
battery from a 5V supply at room temperature. Without
a backside thermal connection, this number could drop
to less than 500mA.
IN Bypass Capacitor
Many types of capacitors can be used for input bypassing;
however, caution must be exercised when using multi-layer
ceramic capacitors. Because of the self-resonant and high
Q characteristics of some types of ceramic capacitors, high
voltage transients can be generated under some start-up
conditions, such as connecting the charger input to a live
power source. For more information, refer to Application
Note 88.
4095 F04
C
FILTER
7
2
CHARGE
CURRENT
MONITOR
CIRCUITRY
R
PROG
LTC4095
PROG
GND
10k
Figure 7. Isolating Capacitive Load on PROG Pin and Filtering
LTC4095
15
4095fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
DC Package
8-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1719 Rev Ø)
2.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
0.64 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
1.37 ±0.10
(2 SIDES)
1
4
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DC8) DFN 0106 REVØ
0.23 ± 0.05
0.45 BSC
0.25 ± 0.05
1.37 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.64 ±0.05
(2 SIDES)
1.15 ±0.05
0.70 ±0.05
2.55 ±0.05
PACKAGE
OUTLINE
0.45 BSC
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER

LTC4095EDC#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Standalone 950mA USB Li-Ion/Polymer Battery Charger in DFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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