Detailed Description
Reset Function/Output
The reset output is typically connected to the reset input
of a µP. A µP’s reset input starts or restarts the µP in a
known state. The MAX6301–MAX6304 µP supervisory
circuits provide the reset logic to prevent code-execution
errors during power-up, power-down, and brownout
conditions (see the
Typical Operating Circuit
).
For the MAX6301/MAX6303, RESET changes from high
to low whenever the monitored voltage (V
IN
) drops
below the reset threshold voltage (V
RST
). RESET
remains low as long as V
IN
is below V
RST
. Once V
IN
exceeds V
RST
, RESET remains low for the reset timeout
period, then goes high. When a reset is asserted due to
a watchdog timeout condition, RESET stays low for the
reset timeout period. Any time reset asserts, the watch-
dog timer clears. At the end of the reset timeout period,
RESET goes high and the watchdog timer is restarted
from zero. If the watchdog timeout period is exceeded
again, then RESET goes low again. This cycle contin-
ues unless WDI receives a transition.
On power-up, once V
CC
reaches 1V, RESET is guaran-
teed to be a logic-low. For information about applica-
tions where V
CC
is less than 1V, see the
Ensuring a
Valid RESET/RESET Output Down to V
CC
= 0V (MAX6303/
MAX6304)
section. As V
CC
rises, RESET remains low.
When V
IN
rises above V
RST
, the reset timer starts and
RESET remains low. When the reset timeout period
ends, RESET goes high.
On power-down, once V
IN
goes below V
RST
, RESET
goes low and is guaranteed to be low until V
CC
drops
below 1V. For information about applications where
V
CC
is less than 1V, see the
Ensuring a Valid
RESET/RESET Output Down to V
CC
= 0V (MAX6303/
MAX6304)
section.
The MAX6302/MAX6304 active-high RESET output is
the inverse of the MAX6301/MAX6303 active-low
RESET output, and is guaranteed valid for V
CC
> 1.31V.
Reset Threshold
These supervisors monitor the voltage on RESET IN.
The MAX6301–MAX6304 have an adjustable reset
threshold voltage (V
RST
) set with an external resistor
voltage-divider (Figure 1). Use the following formula to
calculate V
RST
(the point at which the monitored voltage
triggers a reset):
where V
RST
is the desired reset threshold voltage and
V
TH
is the reset input threshold (1.22V). Resistors R1
and R2 can have very high values to minimize current
consumption. Set R2 to some conveniently high value
(1MΩ, for example) and calculate R1 based on the desired
reset threshold voltage, using the following formula:
Watchdog Timer
The watchdog circuit monitors the µP’s activity. If the µP
does not toggle the watchdog input (WDI) within t
WD
(user selected), reset asserts. The internal watchdog
timer is cleared by reset, by a transition at WDI (which
can detect pulses as short as 30ns), or by a transition
at WDS. The watchdog timer remains cleared while
reset is asserted; as soon as reset is released, the timer
starts counting (Figure 2).
The MAX6301–MAX6304 feature two modes of watchdog
timer operation: normal mode and extended mode. In
normal mode (WDS = GND), the watchdog timeout
period is determined by the value of the capacitor con-
nected between SWT and ground (see the
Selecting
the Reset and Watchdog Timeout Capacitor
section). In
extended mode (WDS = V
CC
), the watchdog timeout
period is multiplied by 500. For example, in the extended
mode, a 1µF capacitor gives a watchdog timeout period
of 22 minutes (see the Extended-Mode Watchdog
Timeout Period vs. C
SWT
graph in the
Typical
Operating Characteristics
).
In extended mode, the watchdog function can be
disabled by leaving WDI unconnected or by three-stating
the driver connected to WDI. In this mode, the watchdog
input is internally driven low during the watchdog timeout
period, then momentarily pulses high, resetting the
