OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADRF5250BCPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15
ADRF5250 Data Sheet
Rev. 0 | Page 10 of 15
65
30
INPUT IP3 (dBm)
35
40
45
50
55
60
0.5 6.0
FREQUENCY (GHz)
1.0
1.5 2.0
2.5
3.0 3.5
4.0 4.5
5.0 5.5
RFC TO RF1
RFC TO RF2
RFC TO RF3
RFC TO RF4
RFC TO RF5
15506-015
Figure 16. Input IP3 vs. Frequency, V
DD
= 3.3 V, V
SS
= 0 V
65
30
INPUT IP3 (dBm)
35
40
45
50
55
60
0.5 6.0
FREQUENCY (GHz)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
15506-016
T
A
= +105°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
Figure 17. Input IP3 vs. Frequency over Temperature,
V
DD
= 3.3 V, V
SS
= 0 V
Data Sheet ADRF5250
Rev. 0 | Page 11 of 15
THEORY OF OPERATION
The ADRF5250 requires a positive supply voltage applied to
the VDD pin and 0 V or −3.3 V supply voltage applied to the
VSS pin. Bypass capacitors are recommended on the supply and
digital control lines to minimize RF coupling. An incorporated
negative supply generator is enabled or disabled depending on
the applied V
SS
supply voltage. Table 4 describes the operation
mode of that negative supply generator.
Table 4. Negative Voltage Generator Operation Mode
V
SS
Test Conditions/Comments
0 V The incorporated negative voltage generator is
enabled
−3.3 V The incorporated negative voltage generator is
disabled
The ADRF5250 is internally matched to 50 Ω at the RF common
port (RFC) and the RF throw ports (RF1 to RF5); therefore, no
external matching components are required. All of the RF ports
are dc-coupled to 0 V, and no dc blocking is required at the RF
ports when the RF line potential is equal to 0 V. The design is
bidirectional; the RF input signal can be applied to the RFC port
while the RF throw port (RF1 to RF5) is output, or vice versa.
The ADRF5250 has a 3-bit, 1.8 V logic-compatible control
interface that is controlled through the V1, V2, and V3 digital
control voltage pins. A small bypassing capacitor is recommended
on these digital signal lines to improve the RF signal isolation.
The V1 and V3 test points correspond to the LSB and MSB of
the digital control interface of the ADRF5250. The modes of the
RF paths are determined as shown in Table 5.
When an RF path is on, the RF signal is conducted equally well in
both directions between its throw port (RFx) and common port
(RFC). Otherwise, each RFx path is terminated to an internal
50 Ω resistor that provides high loss between the insertion loss
path and its throw ports.
Table 5. Control Voltage Truth Table
V
3
V
2
V
1
Mode
Low Low Low All Off
Low Low High RF1 on
Low High Low RF2 on
Low
High
High
RF3 on
High Low Low RF4 on
High Low High RF5 on
High High Low All off
High High High All off
The ideal power-up sequence is as follows:
1. Power up GND.
2. Power up VDD and VSS. The relative order is not
important.
3. Power up the digital control inputs. The relative order of
the logic control inputs is not important. However,
powering the digital control inputs before the VDD supply
can inadvertently forward bias and damage the internal
ESD protection structures.
4. Apply an RF input signal.
ADRF5250 Data Sheet
Rev. 0 | Page 12 of 15
APPLICATIONS INFORMATION
EVALUATION BOARD
Figure 18 and Figure 19 show the top and cross sectional views
of the evaluation board, which uses 4-layer construction with a
copper thickness of 0.5 oz (0.7 mil) and dielectric materials
between each copper layer.
1400mil
2200mil
15506-117
Figure 18. Evaluation Board Layout Top View
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
10mil ROGERS 4350B
10mil ROGERS 4350B
8mil ROGERS 4450F
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil)
TOTAL THICKNESS
~30mil
W = 8mil
G = 10mil
15506-118
Figure 19. Evaluation Board Cross Sectional View
All RF traces are routed on Layer 2; the V1, V3, and VSS dc
traces are routed on Layer 3; the V2 and VDD dc traces are
routed on the top layer; and the other remaining layers are
grounded planes that provide a solid ground for RF transmission
lines. The top and bottom dielectric material are Rogers 4350B,
offering low loss performance. The middle dielectric material is
Rogers 4450F and is used to achieve an overall board thickness
of 30 mil. The RF transmission lines were designed using a
coplanar waveguide (CPWG) model with a width of 8 mil and
ground spacing of 10 mil for a characteristic impedance of 50 Ω.
For optimal RF and thermal grounding, as many plated through
vias as possible are arranged around the transmission lines and
under the exposed pad of the package.
Figure 20 shows the actual ADRF5250 evaluation board with
component placement. Two power supply ports are connected
to the VDD and VSS test points, TP3 and TP5, and the ground
reference is connected to the GND test point, TP6. On the digital
control and VDD supply traces, bypass capacitors are used.
15506-018
Figure 20. ADRF5250-EVALZ Evaluation Board
Three control ports are connected to the V1, V2, and V3 test
points, TP1, TP2, and TP4, respectively. On each control trace,
a resistor position is available to improve the isolation between
the RF and control signals. The RF ports are connected to the
RFC, RF1, RF2, RF3, RF4, and RF5 connectors (J6, J8, J7, J5, J2,
and J1), which are end launch jack SMA RF connectors. A
through transmission line that connects unpopulated RF
connectors (J3 and J4) is also available to measure the loss of
the PCB. Figure 22 and Table 6 show the evaluation board
schematic and bill of materials, respectively.
The evaluation board shown in Figure 20 is available for order
from the Analog Devices, Inc., website at www.analog.com.
P1-P3P4-P6P7-P9P10-P12P13-P15

ADRF5250BCPZRL

Mfr. #:
Buy ADRF5250BCPZRL
Manufacturer:
Analog Devices Inc.
Description:
RF Switch ICs 0.1-6GHz High Isolation SP5T
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet