January 1995 4
Philips Semiconductors Product specification
Dual JK flip-flop
HEF4027B
flip-flops
C
D
→ O 5 75 150 ns 48 ns + (0,55 ns/pF) C
L
LOW to HIGH 10 t
PLH
35 70 ns 24 ns + (0,23 ns/pF) C
L
15 25 50 ns 17 ns + (0,16 ns/pF) C
L
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
L
HIGH to LOW 10 t
THL
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
5 60 120 ns 10 ns + (1,0 ns/pF) C
L
LOW to HIGH 10 t
TLH
30 60 ns 9 ns + (0,42 ns/pF) C
L
15 20 40 ns 6 ns + (0,28 ns/pF) C
L
Set-up time 5 50 25 ns
see also waveforms
Figs 4 and 5
J,K → CP 10 t
su
30 10 ns
15 20 5 ns
Hold time 5 25 0 ns
J,K → CP 10 t
hold
20 0 ns
15 15 5 ns
Minimum clock 5 80 40 ns
pulse width; LOW 10 t
WCPL
30 15 ns
15 24 12 ns
Minimum S
D
,C
D
5
t
WSDH,
t
WCDH
90 45 ns
pulse width; HIGH 10 40 20 ns
15 30 15 ns
Recovery time 5
t
RSD,
t
RCD
20 −15 ns
for S
D
,C
D
10 15 −10 ns
15 10 −5ns
Maximum clock 5 4 8 MHz
see also waveforms
Fig.4
pulse frequency 10 f
max
12 25 MHz
J = K = HIGH 15 15 30 MHz
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 900 f
i
+∑(f
o
C
L
) × V
DD
2
where
dissipation per 10 4 500 f
i
+∑(f
o
C
L
) × V
DD
2
f
i
= input freq. (MHz)
package (P) 15 13 200 f
i
+∑(f
o
C
L
) × V
DD
2
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑ (f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
V
DD
V
SYMBOL MIN. TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
